Reference

Zilog Z8000

182 instructions, words big-endian. Generated from crates/isa/src/z8000.rs.

The Z8000 is specified family by family, because the families genuinely differ: a block move carries a shape and a control nibble, an I/O instruction carries a direction, a shift carries whether its count is a following word. The tables below keep that structure, and each shows the columns its family actually has.

Sizes are the operand widths a mnemonic assembles at. Rn is a word register, @Rn an indirect one, addr a direct address and addr(Rn) an indexed one.

Arithmetic, logic and load

The dyadic family: a destination register and a source in any of the addressing modes listed.

Mnemonic Base Size Source modes Summary
ADD 01 word #n, @Rn, addr, addr(Rn), Rn Add
ADDB 00 byte #n, @Rn, addr, addr(Rn), Rn Add byte
SUB 03 word #n, @Rn, addr, addr(Rn), Rn Subtract
SUBB 02 byte #n, @Rn, addr, addr(Rn), Rn Subtract byte
OR 05 word #n, @Rn, addr, addr(Rn), Rn Or
ORB 04 byte #n, @Rn, addr, addr(Rn), Rn Or byte
AND 07 word #n, @Rn, addr, addr(Rn), Rn And
ANDB 06 byte #n, @Rn, addr, addr(Rn), Rn And byte
XOR 09 word #n, @Rn, addr, addr(Rn), Rn Exclusive or
XORB 08 byte #n, @Rn, addr, addr(Rn), Rn Exclusive or byte
CP 0B word #n, @Rn, addr, addr(Rn), Rn Compare
CPB 0A byte #n, @Rn, addr, addr(Rn), Rn Compare byte
LD 21 word #n, @Rn, addr, addr(Rn), Rn Load
LDB 20 byte #n, @Rn, addr, addr(Rn), Rn Load byte
ADC 35 word Rn Add with carry
ADCB 34 byte Rn Add with carry byte
SBC 37 word Rn Subtract with carry
SBCB 36 byte Rn Subtract with carry byte
CPL 10 long #n, @Rn, addr, addr(Rn), Rn Compare long
SUBL 12 long #n, @Rn, addr, addr(Rn), Rn Subtract long
LDL 14 long #n, @Rn, addr, addr(Rn), Rn Load long
ADDL 16 long #n, @Rn, addr, addr(Rn), Rn Add long
EX 2D word @Rn, addr, addr(Rn), Rn Exchange
EXB 2C byte @Rn, addr, addr(Rn), Rn Exchange byte
LDA 36 address addr, addr(Rn) Load address

Program control

Mnemonic Base Shape Summary
JP 001E A memory operand, with a condition code in the low nibble Jump
CALL 001F A memory operand, with a condition code in the low nibble Call
JR 00E0 A condition code, then a word-scaled signed 8-bit PC offset Jump relative
RET 9E00 A condition code only Return
DJNZ 00F0 A register, then a 7-bit backward word offset Decrement and jump if not zero
DBJNZ 00F0 A register, then a 7-bit backward word offset Decrement byte and jump if not zero
CALR 00D0 A 12-bit backward word offset Call relative

Single-operand

Mnemonic Base Sub-op Size Summary
COM 0D 0 word Complement
COMB 0C 0 byte Complement byte
NEG 0D 2 word Negate
NEGB 0C 2 byte Negate byte
TEST 0D 4 word Test
TESTB 0C 4 byte Test byte
TSET 0D 6 word Test and set
TSETB 0C 6 byte Test and set byte
CLR 0D 8 word Clear
CLRB 0C 8 byte Clear byte
INC 29 0 word Increment
INCB 28 0 byte Increment byte
DEC 2B 0 word Decrement
DECB 2A 0 byte Decrement byte

Stack

Mnemonic Base Size Summary
PUSH 13 word Push
PUSHL 11 long Push long
POP 17 word Pop
POPL 15 long Pop long

Shift and rotate

Mnemonic Base Size Count Summary
SLA 33 word A signed count word follows — positive shifts left, negative right Shift left arithmetic
SRA 33 word A signed count word follows — positive shifts left, negative right Shift right arithmetic
SLL 33 word A signed count word follows — positive shifts left, negative right Shift left logical
SRL 33 word A signed count word follows — positive shifts left, negative right Shift right logical
SLAL 33 long A signed count word follows — positive shifts left, negative right Shift left arithmetic long
SRAL 33 long A signed count word follows — positive shifts left, negative right Shift right arithmetic long
SLLL 33 long A signed count word follows — positive shifts left, negative right Shift left logical long
SRLL 33 long A signed count word follows — positive shifts left, negative right Shift right logical long
SLAB 32 byte A signed count word follows — positive shifts left, negative right Shift left arithmetic byte
SRAB 32 byte A signed count word follows — positive shifts left, negative right Shift right arithmetic byte
SLLB 32 byte A signed count word follows — positive shifts left, negative right Shift left logical byte
SRLB 32 byte A signed count word follows — positive shifts left, negative right Shift right logical byte
RL 33 word By one or two, packed into the low nibble; no count word Rotate left
RR 33 word By one or two, packed into the low nibble; no count word Rotate right
RLC 33 word By one or two, packed into the low nibble; no count word Rotate left through carry
RRC 33 word By one or two, packed into the low nibble; no count word Rotate right through carry
RLB 32 byte By one or two, packed into the low nibble; no count word Rotate left byte
RRB 32 byte By one or two, packed into the low nibble; no count word Rotate right byte
RLCB 32 byte By one or two, packed into the low nibble; no count word Rotate left through carry byte
RRCB 32 byte By one or two, packed into the low nibble; no count word Rotate right through carry byte

Sign extend

Mnemonic Sub-op Size Summary
EXTSB 0 word Extend sign byte
EXTS A long Extend sign word
EXTSL 7 quad Extend sign long

Bit

Mnemonic Base Size Summary
BIT 27 word Test bit
BITB 26 byte Test bit byte
SET 25 word Set bit
SETB 24 byte Set bit byte
RES 23 word Reset bit
RESB 22 byte Reset bit byte

Multiply and divide

Mnemonic Base Destination Source Summary
MULT 19 long word Multiply (word)
MULTL 18 quad long Multiply long
DIV 1B long word Divide (word)
DIVL 1A quad long Divide long

Block move and compare

Mnemonic Base Size Operands Summary
LDI 3B word Source pointer, destination pointer, count register Load and increment
LDIR 3B word Source pointer, destination pointer, count register Load, increment and repeat
LDD 3B word Source pointer, destination pointer, count register Load and decrement
LDDR 3B word Source pointer, destination pointer, count register Load, decrement and repeat
LDIB 3A byte Source pointer, destination pointer, count register Load byte and increment
LDIRB 3A byte Source pointer, destination pointer, count register Load byte, increment and repeat
LDDB 3A byte Source pointer, destination pointer, count register Load byte and decrement
LDDRB 3A byte Source pointer, destination pointer, count register Load byte, decrement and repeat
CPI 3B word Source pointer, a data register, count and condition Compare and increment
CPIR 3B word Source pointer, a data register, count and condition Compare, increment and repeat
CPD 3B word Source pointer, a data register, count and condition Compare and decrement
CPDR 3B word Source pointer, a data register, count and condition Compare, decrement and repeat
CPIB 3A byte Source pointer, a data register, count and condition Compare byte and increment
CPIRB 3A byte Source pointer, a data register, count and condition Compare byte, increment and repeat
CPDB 3A byte Source pointer, a data register, count and condition Compare byte and decrement
CPDRB 3A byte Source pointer, a data register, count and condition Compare byte, decrement and repeat
CPSI 3B word Two pointers, with a condition code in the control nibble Compare string and increment
CPSIR 3B word Two pointers, with a condition code in the control nibble Compare string, increment and repeat
CPSD 3B word Two pointers, with a condition code in the control nibble Compare string and decrement
CPSDR 3B word Two pointers, with a condition code in the control nibble Compare string, decrement and repeat
CPSIB 3A byte Two pointers, with a condition code in the control nibble Compare string byte and increment
CPSIRB 3A byte Two pointers, with a condition code in the control nibble Compare string byte, increment and repeat
CPSDB 3A byte Two pointers, with a condition code in the control nibble Compare string byte and decrement
CPSDRB 3A byte Two pointers, with a condition code in the control nibble Compare string byte, decrement and repeat
TRIB 38 byte Destination pointer first, then source — the reverse of a load Translate and increment
TRIRB 38 byte Destination pointer first, then source — the reverse of a load Translate, increment and repeat
TRDB 38 byte Destination pointer first, then source — the reverse of a load Translate and decrement
TRDRB 38 byte Destination pointer first, then source — the reverse of a load Translate, decrement and repeat
TRTIB 38 byte Destination pointer first, then source — the reverse of a load Translate and test, increment
TRTIRB 38 byte Destination pointer first, then source — the reverse of a load Translate and test, increment and repeat
TRTDB 38 byte Destination pointer first, then source — the reverse of a load Translate and test, decrement
TRTDRB 38 byte Destination pointer first, then source — the reverse of a load Translate and test, decrement and repeat

Input and output

Mnemonic Direction Size Summary
IN in word Input
INB in byte Input byte
SIN in word Special input
SINB in byte Special input byte
OUT out word Output
OUTB out byte Output byte
SOUT out word Special output
SOUTB out byte Special output byte

Block input and output

Mnemonic Size Summary
INI word Input and increment
INIR word Input, increment and repeat
IND word Input and decrement
INDR word Input, decrement and repeat
INIB byte Input byte and increment
INIRB byte Input byte, increment and repeat
INDB byte Input byte and decrement
INDRB byte Input byte, decrement and repeat
OUTI word Output and increment
OTIR word Output, increment and repeat
OUTD word Output and decrement
OTDR word Output, decrement and repeat
OUTIB byte Output byte and increment
OTIRB byte Output byte, increment and repeat
OUTDB byte Output byte and decrement
OTDRB byte Output byte, decrement and repeat
SINI word Special input and increment
SINIR word Special input, increment and repeat
SIND word Special input and decrement
SINDR word Special input, decrement and repeat
SINIB byte Special input byte and increment
SINIRB byte Special input byte, increment and repeat
SINDB byte Special input byte and decrement
SINDRB byte Special input byte, decrement and repeat
SOUTI word Special output and increment
SOTIR word Special output, increment and repeat
SOUTD word Special output and decrement
SOTDR word Special output, decrement and repeat
SOUTIB byte Special output byte and increment
SOTIRB byte Special output byte, increment and repeat
SOUTDB byte Special output byte and decrement
SOTDRB byte Special output byte, decrement and repeat

CPU control

Mnemonic Operands Summary
NOP A fixed two-byte word, no operand No operation
HALT A fixed two-byte word, no operand Halt
IRET A fixed two-byte word, no operand Interrupt return
MSET A fixed two-byte word, no operand Multi-micro set
MRES A fixed two-byte word, no operand Multi-micro reset
MBIT A fixed two-byte word, no operand Test multi-micro bit
MREQ A register in the high nibble Multi-micro request
SETFLG A flag mask in the high nibble Set flags
RESFLG A flag mask in the high nibble Reset flags
COMFLG A flag mask in the high nibble Complement flags
EI An interrupt-source list Enable interrupt
DI An interrupt-source list Disable interrupt
LDCTL A register and a control register Load control register
LDCTLB A register and a control register Load control register byte
LDPS A memory operand holding a program status Load program status
SC A system-call number, 0-255 System call

Other

Mnemonic Top Size Operands Summary
TCC AF word A condition code and a register Test condition code
TCCB AE byte A condition code and a register Test condition code byte
LDK BD word A register and a 4-bit constant Load constant
RLDB BE byte Two byte registers, rotated a digit at a time Rotate left digit
RRDB BC byte Two byte registers, rotated a digit at a time Rotate right digit
LDR 31 word A register and a PC-relative address Load relative
LDRB 30 byte A register and a PC-relative address Load relative byte
LDRL 35 long A register and a PC-relative address Load relative long

Sources

Encodings on this page were taken from:

  • Z8000 CPU Technical Manual — Zilog, 1983