Reference

Intel 8048 (MCS-48)

58 mnemonics, 214 encoded forms, operands little-endian. Generated from crates/isa/src/i8048.rs.

Cycle counts show the base cost; +p is an extra cycle when an indexed access crosses a page boundary, +t when a branch is taken.

ADD

Add to A

Mode Opcode Operands Bytes Cycles Flags
a,r0 68 — 1 1 C AC
a,r1 69 — 1 1 C AC
a,r2 6A — 1 1 C AC
a,r3 6B — 1 1 C AC
a,r4 6C — 1 1 C AC
a,r5 6D — 1 1 C AC
a,r6 6E — 1 1 C AC
a,r7 6F — 1 1 C AC
a,@r0 60 — 1 1 C AC
a,@r1 61 — 1 1 C AC
a,#N 03 imm8 2 2 C AC

ADDC

Add with carry to A

Mode Opcode Operands Bytes Cycles Flags
a,r0 78 — 1 1 C AC
a,r1 79 — 1 1 C AC
a,r2 7A — 1 1 C AC
a,r3 7B — 1 1 C AC
a,r4 7C — 1 1 C AC
a,r5 7D — 1 1 C AC
a,r6 7E — 1 1 C AC
a,r7 7F — 1 1 C AC
a,@r0 70 — 1 1 C AC
a,@r1 71 — 1 1 C AC
a,#N 13 imm8 2 2 C AC

ANL

AND with A

Mode Opcode Operands Bytes Cycles Flags
a,r0 58 — 1 1 —
a,r1 59 — 1 1 —
a,r2 5A — 1 1 —
a,r3 5B — 1 1 —
a,r4 5C — 1 1 —
a,r5 5D — 1 1 —
a,r6 5E — 1 1 —
a,r7 5F — 1 1 —
a,@r0 50 — 1 1 —
a,@r1 51 — 1 1 —
a,#N 53 imm8 2 2 —
bus,#N 98 imm8 2 2 —
p1,#N 99 imm8 2 2 —
p2,#N 9A imm8 2 2 —

ORL

OR with A

Mode Opcode Operands Bytes Cycles Flags
a,r0 48 — 1 1 —
a,r1 49 — 1 1 —
a,r2 4A — 1 1 —
a,r3 4B — 1 1 —
a,r4 4C — 1 1 —
a,r5 4D — 1 1 —
a,r6 4E — 1 1 —
a,r7 4F — 1 1 —
a,@r0 40 — 1 1 —
a,@r1 41 — 1 1 —
a,#N 43 imm8 2 2 —
bus,#N 88 imm8 2 2 —
p1,#N 89 imm8 2 2 —
p2,#N 8A imm8 2 2 —

XRL

XOR with A

Mode Opcode Operands Bytes Cycles Flags
a,r0 D8 — 1 1 —
a,r1 D9 — 1 1 —
a,r2 DA — 1 1 —
a,r3 DB — 1 1 —
a,r4 DC — 1 1 —
a,r5 DD — 1 1 —
a,r6 DE — 1 1 —
a,r7 DF — 1 1 —
a,@r0 D0 — 1 1 —
a,@r1 D1 — 1 1 —
a,#N D3 imm8 2 2 —

INC

Increment

Mode Opcode Operands Bytes Cycles Flags
a 17 — 1 1 —
r0 18 — 1 1 —
r1 19 — 1 1 —
r2 1A — 1 1 —
r3 1B — 1 1 —
r4 1C — 1 1 —
r5 1D — 1 1 —
r6 1E — 1 1 —
r7 1F — 1 1 —
@r0 10 — 1 1 —
@r1 11 — 1 1 —

DEC

Decrement

Mode Opcode Operands Bytes Cycles Flags
a 07 — 1 1 —
r0 C8 — 1 1 —
r1 C9 — 1 1 —
r2 CA — 1 1 —
r3 CB — 1 1 —
r4 CC — 1 1 —
r5 CD — 1 1 —
r6 CE — 1 1 —
r7 CF — 1 1 —

CLR

Clear

Mode Opcode Operands Bytes Cycles Flags
a 27 — 1 1 —
c 97 — 1 1 C
f0 85 — 1 1 —
f1 A5 — 1 1 —

CPL

Complement

Mode Opcode Operands Bytes Cycles Flags
a 37 — 1 1 —
c A7 — 1 1 C
f0 95 — 1 1 —
f1 B5 — 1 1 —

DA

Decimal-adjust A

Mode Opcode Operands Bytes Cycles Flags
a 57 — 1 1 —

SWAP

Swap nibbles of A

Mode Opcode Operands Bytes Cycles Flags
a 47 — 1 1 —

RL

Rotate A left

Mode Opcode Operands Bytes Cycles Flags
a E7 — 1 1 —

RLC

Rotate A left through carry

Mode Opcode Operands Bytes Cycles Flags
a F7 — 1 1 —

RR

Rotate A right

Mode Opcode Operands Bytes Cycles Flags
a 77 — 1 1 —

RRC

Rotate A right through carry

Mode Opcode Operands Bytes Cycles Flags
a 67 — 1 1 —

IN

Input port to A

Mode Opcode Operands Bytes Cycles Flags
a,p1 09 — 1 1 —
a,p2 0A — 1 1 —

INS

Input BUS to A

Mode Opcode Operands Bytes Cycles Flags
a,bus 08 — 1 1 —

OUTL

Output A to port

Mode Opcode Operands Bytes Cycles Flags
bus,a 02 — 1 1 —
p1,a 39 — 1 1 —
p2,a 3A — 1 1 —

MOVD

Move 4-bit port

Mode Opcode Operands Bytes Cycles Flags
a,p4 0C — 1 1 —
a,p5 0D — 1 1 —
a,p6 0E — 1 1 —
a,p7 0F — 1 1 —
p4,a 3C — 1 1 —
p5,a 3D — 1 1 —
p6,a 3E — 1 1 —
p7,a 3F — 1 1 —

ANLD

AND A to 4-bit port

Mode Opcode Operands Bytes Cycles Flags
p4,a 9C — 1 1 —
p5,a 9D — 1 1 —
p6,a 9E — 1 1 —
p7,a 9F — 1 1 —

ORLD

OR A to 4-bit port

Mode Opcode Operands Bytes Cycles Flags
p4,a 8C — 1 1 —
p5,a 8D — 1 1 —
p6,a 8E — 1 1 —
p7,a 8F — 1 1 —

MOV

Move

Mode Opcode Operands Bytes Cycles Flags
a,r0 F8 — 1 1 —
a,r1 F9 — 1 1 —
a,r2 FA — 1 1 —
a,r3 FB — 1 1 —
a,r4 FC — 1 1 —
a,r5 FD — 1 1 —
a,r6 FE — 1 1 —
a,r7 FF — 1 1 —
a,@r0 F0 — 1 1 —
a,@r1 F1 — 1 1 —
a,#N 23 imm8 2 2 —
r0,a A8 — 1 1 —
r1,a A9 — 1 1 —
r2,a AA — 1 1 —
r3,a AB — 1 1 —
r4,a AC — 1 1 —
r5,a AD — 1 1 —
r6,a AE — 1 1 —
r7,a AF — 1 1 —
@r0,a A0 — 1 1 —
@r1,a A1 — 1 1 —
r0,#N B8 imm8 2 2 —
r1,#N B9 imm8 2 2 —
r2,#N BA imm8 2 2 —
r3,#N BB imm8 2 2 —
r4,#N BC imm8 2 2 —
r5,#N BD imm8 2 2 —
r6,#N BE imm8 2 2 —
r7,#N BF imm8 2 2 —
@r0,#N B0 imm8 2 2 —
@r1,#N B1 imm8 2 2 —
a,psw C7 — 1 1 —
psw,a D7 — 1 1 —
a,t 42 — 1 1 —
t,a 62 — 1 1 —

XCH

Exchange A

Mode Opcode Operands Bytes Cycles Flags
a,r0 28 — 1 1 —
a,r1 29 — 1 1 —
a,r2 2A — 1 1 —
a,r3 2B — 1 1 —
a,r4 2C — 1 1 —
a,r5 2D — 1 1 —
a,r6 2E — 1 1 —
a,r7 2F — 1 1 —
a,@r0 20 — 1 1 —
a,@r1 21 — 1 1 —

XCHD

Exchange A low nibble

Mode Opcode Operands Bytes Cycles Flags
a,@r0 30 — 1 1 —
a,@r1 31 — 1 1 —

MOVX

Move external data

Mode Opcode Operands Bytes Cycles Flags
a,@r0 80 — 1 1 —
a,@r1 81 — 1 1 —
@r0,a 90 — 1 1 —
@r1,a 91 — 1 1 —

MOVP

Move program memory to A

Mode Opcode Operands Bytes Cycles Flags
a,@a A3 — 1 1 —

MOVP3

Move page-3 program memory

Mode Opcode Operands Bytes Cycles Flags
a,@a E3 — 1 1 —

JMPP

Jump indirect within page

Mode Opcode Operands Bytes Cycles Flags
@a B3 — 1 1 —

RET

Return

Mode Opcode Operands Bytes Cycles Flags
83 — 1 2 —

RETR

Return, restore PSW

Mode Opcode Operands Bytes Cycles Flags
93 — 1 2 —

JC

Jump if carry

Mode Opcode Operands Bytes Cycles Flags
rel F6 imm8 2 2 —

JNC

Jump if no carry

Mode Opcode Operands Bytes Cycles Flags
rel E6 imm8 2 2 —

JZ

Jump if A zero

Mode Opcode Operands Bytes Cycles Flags
rel C6 imm8 2 2 —

JNZ

Jump if A not zero

Mode Opcode Operands Bytes Cycles Flags
rel 96 imm8 2 2 —

JT0

Jump if T0 high

Mode Opcode Operands Bytes Cycles Flags
rel 36 imm8 2 2 —

JNT0

Jump if T0 low

Mode Opcode Operands Bytes Cycles Flags
rel 26 imm8 2 2 —

JT1

Jump if T1 high

Mode Opcode Operands Bytes Cycles Flags
rel 56 imm8 2 2 —

JNT1

Jump if T1 low

Mode Opcode Operands Bytes Cycles Flags
rel 46 imm8 2 2 —

JF0

Jump if F0 set

Mode Opcode Operands Bytes Cycles Flags
rel B6 imm8 2 2 —

JF1

Jump if F1 set

Mode Opcode Operands Bytes Cycles Flags
rel 76 imm8 2 2 —

JTF

Jump if timer flag

Mode Opcode Operands Bytes Cycles Flags
rel 16 imm8 2 2 —

JNI

Jump if interrupt

Mode Opcode Operands Bytes Cycles Flags
rel 86 imm8 2 2 —

JB0

Jump if A bit 0 set

Mode Opcode Operands Bytes Cycles Flags
rel 12 imm8 2 2 —

JB1

Jump if A bit 1 set

Mode Opcode Operands Bytes Cycles Flags
rel 32 imm8 2 2 —

JB2

Jump if A bit 2 set

Mode Opcode Operands Bytes Cycles Flags
rel 52 imm8 2 2 —

JB3

Jump if A bit 3 set

Mode Opcode Operands Bytes Cycles Flags
rel 72 imm8 2 2 —

JB4

Jump if A bit 4 set

Mode Opcode Operands Bytes Cycles Flags
rel 92 imm8 2 2 —

JB5

Jump if A bit 5 set

Mode Opcode Operands Bytes Cycles Flags
rel B2 imm8 2 2 —

JB6

Jump if A bit 6 set

Mode Opcode Operands Bytes Cycles Flags
rel D2 imm8 2 2 —

JB7

Jump if A bit 7 set

Mode Opcode Operands Bytes Cycles Flags
rel F2 imm8 2 2 —

DJNZ

Decrement and jump if not zero

Mode Opcode Operands Bytes Cycles Flags
r0,rel E8 imm8 2 2 —
r1,rel E9 imm8 2 2 —
r2,rel EA imm8 2 2 —
r3,rel EB imm8 2 2 —
r4,rel EC imm8 2 2 —
r5,rel ED imm8 2 2 —
r6,rel EE imm8 2 2 —
r7,rel EF imm8 2 2 —

EN

Enable

Mode Opcode Operands Bytes Cycles Flags
i 05 — 1 1 —
tcnti 25 — 1 1 —

DIS

Disable

Mode Opcode Operands Bytes Cycles Flags
i 15 — 1 1 —
tcnti 35 — 1 1 —

SEL

Select bank

Mode Opcode Operands Bytes Cycles Flags
rb0 C5 — 1 1 —
rb1 D5 — 1 1 —
mb0 E5 — 1 1 —
mb1 F5 — 1 1 —

ENT0

Enable T0 clock output

Mode Opcode Operands Bytes Cycles Flags
clk 75 — 1 1 —

STRT

Start timer/counter

Mode Opcode Operands Bytes Cycles Flags
t 55 — 1 1 —
cnt 45 — 1 1 —

STOP

Stop timer/counter

Mode Opcode Operands Bytes Cycles Flags
tcnt 65 — 1 1 —

NOP

No operation

Mode Opcode Operands Bytes Cycles Flags
00 — 1 1 —

Machines

Magnavox Odyssey², Commodore Amiga

Sources

Encodings on this page were taken from:

  • MCS-48 Family User’s Manual — Intel, 1978