Reference

Intel 8080

78 mnemonics, 244 encoded forms, operands little-endian. Generated from crates/isa/src/i8080.rs.

Cycle counts show the base cost; +p is an extra cycle when an indexed access crosses a page boundary, +t when a branch is taken.

NOP

No operation

Mode Opcode Operands Bytes Cycles Flags
00 — 1 4 —

HLT

Halt

Mode Opcode Operands Bytes Cycles Flags
76 — 1 4 —

EI

Enable interrupts

Mode Opcode Operands Bytes Cycles Flags
FB — 1 4 —

DI

Disable interrupts

Mode Opcode Operands Bytes Cycles Flags
F3 — 1 4 —

XCHG

Exchange DE and HL

Mode Opcode Operands Bytes Cycles Flags
EB — 1 4 —

XTHL

Exchange top of stack with HL

Mode Opcode Operands Bytes Cycles Flags
E3 — 1 4 —

SPHL

Move HL to SP

Mode Opcode Operands Bytes Cycles Flags
F9 — 1 4 —

PCHL

Move HL to PC

Mode Opcode Operands Bytes Cycles Flags
E9 — 1 4 —

RLC

Rotate A left

Mode Opcode Operands Bytes Cycles Flags
07 — 1 4 C

RRC

Rotate A right

Mode Opcode Operands Bytes Cycles Flags
0F — 1 4 C

RAL

Rotate A left through carry

Mode Opcode Operands Bytes Cycles Flags
17 — 1 4 C

RAR

Rotate A right through carry

Mode Opcode Operands Bytes Cycles Flags
1F — 1 4 C

DAA

Decimal adjust A

Mode Opcode Operands Bytes Cycles Flags
27 — 1 4 SZAPC

CMA

Complement A

Mode Opcode Operands Bytes Cycles Flags
2F — 1 4 —

STC

Set carry

Mode Opcode Operands Bytes Cycles Flags
37 — 1 4 C

CMC

Complement carry

Mode Opcode Operands Bytes Cycles Flags
3F — 1 4 C

MOV

Move register

Mode Opcode Operands Bytes Cycles Flags
b,b 40 — 1 5 —
b,c 41 — 1 5 —
b,d 42 — 1 5 —
b,e 43 — 1 5 —
b,h 44 — 1 5 —
b,l 45 — 1 5 —
b,m 46 — 1 7 —
b,a 47 — 1 5 —
c,b 48 — 1 5 —
c,c 49 — 1 5 —
c,d 4A — 1 5 —
c,e 4B — 1 5 —
c,h 4C — 1 5 —
c,l 4D — 1 5 —
c,m 4E — 1 7 —
c,a 4F — 1 5 —
d,b 50 — 1 5 —
d,c 51 — 1 5 —
d,d 52 — 1 5 —
d,e 53 — 1 5 —
d,h 54 — 1 5 —
d,l 55 — 1 5 —
d,m 56 — 1 7 —
d,a 57 — 1 5 —
e,b 58 — 1 5 —
e,c 59 — 1 5 —
e,d 5A — 1 5 —
e,e 5B — 1 5 —
e,h 5C — 1 5 —
e,l 5D — 1 5 —
e,m 5E — 1 7 —
e,a 5F — 1 5 —
h,b 60 — 1 5 —
h,c 61 — 1 5 —
h,d 62 — 1 5 —
h,e 63 — 1 5 —
h,h 64 — 1 5 —
h,l 65 — 1 5 —
h,m 66 — 1 7 —
h,a 67 — 1 5 —
l,b 68 — 1 5 —
l,c 69 — 1 5 —
l,d 6A — 1 5 —
l,e 6B — 1 5 —
l,h 6C — 1 5 —
l,l 6D — 1 5 —
l,m 6E — 1 7 —
l,a 6F — 1 5 —
m,b 70 — 1 7 —
m,c 71 — 1 7 —
m,d 72 — 1 7 —
m,e 73 — 1 7 —
m,h 74 — 1 7 —
m,l 75 — 1 7 —
m,a 77 — 1 7 —
a,b 78 — 1 5 —
a,c 79 — 1 5 —
a,d 7A — 1 5 —
a,e 7B — 1 5 —
a,h 7C — 1 5 —
a,l 7D — 1 5 —
a,m 7E — 1 7 —
a,a 7F — 1 5 —

MVI

Move immediate

Mode Opcode Operands Bytes Cycles Flags
b,N 06 imm8 2 7 —
c,N 0E imm8 2 7 —
d,N 16 imm8 2 7 —
e,N 1E imm8 2 7 —
h,N 26 imm8 2 7 —
l,N 2E imm8 2 7 —
m,N 36 imm8 2 10 —
a,N 3E imm8 2 7 —

LXI

Load register pair immediate

Mode Opcode Operands Bytes Cycles Flags
b,NN 01 addr16 3 10 —
d,NN 11 addr16 3 10 —
h,NN 21 addr16 3 10 —
sp,NN 31 addr16 3 10 —

LDA

Load A direct

Mode Opcode Operands Bytes Cycles Flags
NN 3A addr16 3 10 —

STA

Store A direct

Mode Opcode Operands Bytes Cycles Flags
NN 32 addr16 3 10 —

LHLD

Load HL direct

Mode Opcode Operands Bytes Cycles Flags
NN 2A addr16 3 10 —

SHLD

Store HL direct

Mode Opcode Operands Bytes Cycles Flags
NN 22 addr16 3 10 —

LDAX

Load A indirect

Mode Opcode Operands Bytes Cycles Flags
b 0A — 1 7 —
d 1A — 1 7 —

STAX

Store A indirect

Mode Opcode Operands Bytes Cycles Flags
b 02 — 1 7 —
d 12 — 1 7 —

ADD

Add register

Mode Opcode Operands Bytes Cycles Flags
b 80 — 1 4 SZAPC
c 81 — 1 4 SZAPC
d 82 — 1 4 SZAPC
e 83 — 1 4 SZAPC
h 84 — 1 4 SZAPC
l 85 — 1 4 SZAPC
m 86 — 1 7 SZAPC
a 87 — 1 4 SZAPC

ADC

Add register with carry

Mode Opcode Operands Bytes Cycles Flags
b 88 — 1 4 SZAPC
c 89 — 1 4 SZAPC
d 8A — 1 4 SZAPC
e 8B — 1 4 SZAPC
h 8C — 1 4 SZAPC
l 8D — 1 4 SZAPC
m 8E — 1 7 SZAPC
a 8F — 1 4 SZAPC

SUB

Subtract register

Mode Opcode Operands Bytes Cycles Flags
b 90 — 1 4 SZAPC
c 91 — 1 4 SZAPC
d 92 — 1 4 SZAPC
e 93 — 1 4 SZAPC
h 94 — 1 4 SZAPC
l 95 — 1 4 SZAPC
m 96 — 1 7 SZAPC
a 97 — 1 4 SZAPC

SBB

Subtract register with borrow

Mode Opcode Operands Bytes Cycles Flags
b 98 — 1 4 SZAPC
c 99 — 1 4 SZAPC
d 9A — 1 4 SZAPC
e 9B — 1 4 SZAPC
h 9C — 1 4 SZAPC
l 9D — 1 4 SZAPC
m 9E — 1 7 SZAPC
a 9F — 1 4 SZAPC

ANA

AND register

Mode Opcode Operands Bytes Cycles Flags
b A0 — 1 4 SZAPC
c A1 — 1 4 SZAPC
d A2 — 1 4 SZAPC
e A3 — 1 4 SZAPC
h A4 — 1 4 SZAPC
l A5 — 1 4 SZAPC
m A6 — 1 7 SZAPC
a A7 — 1 4 SZAPC

XRA

XOR register

Mode Opcode Operands Bytes Cycles Flags
b A8 — 1 4 SZAPC
c A9 — 1 4 SZAPC
d AA — 1 4 SZAPC
e AB — 1 4 SZAPC
h AC — 1 4 SZAPC
l AD — 1 4 SZAPC
m AE — 1 7 SZAPC
a AF — 1 4 SZAPC

ORA

OR register

Mode Opcode Operands Bytes Cycles Flags
b B0 — 1 4 SZAPC
c B1 — 1 4 SZAPC
d B2 — 1 4 SZAPC
e B3 — 1 4 SZAPC
h B4 — 1 4 SZAPC
l B5 — 1 4 SZAPC
m B6 — 1 7 SZAPC
a B7 — 1 4 SZAPC

CMP

Compare register

Mode Opcode Operands Bytes Cycles Flags
b B8 — 1 4 SZAPC
c B9 — 1 4 SZAPC
d BA — 1 4 SZAPC
e BB — 1 4 SZAPC
h BC — 1 4 SZAPC
l BD — 1 4 SZAPC
m BE — 1 7 SZAPC
a BF — 1 4 SZAPC

ADI

Add immediate

Mode Opcode Operands Bytes Cycles Flags
N C6 imm8 2 7 SZAPC

ACI

Add immediate with carry

Mode Opcode Operands Bytes Cycles Flags
N CE imm8 2 7 SZAPC

SUI

Subtract immediate

Mode Opcode Operands Bytes Cycles Flags
N D6 imm8 2 7 SZAPC

SBI

Subtract immediate with borrow

Mode Opcode Operands Bytes Cycles Flags
N DE imm8 2 7 SZAPC

ANI

AND immediate

Mode Opcode Operands Bytes Cycles Flags
N E6 imm8 2 7 SZAPC

XRI

XOR immediate

Mode Opcode Operands Bytes Cycles Flags
N EE imm8 2 7 SZAPC

ORI

OR immediate

Mode Opcode Operands Bytes Cycles Flags
N F6 imm8 2 7 SZAPC

CPI

Compare immediate

Mode Opcode Operands Bytes Cycles Flags
N FE imm8 2 7 SZAPC

INR

Increment register

Mode Opcode Operands Bytes Cycles Flags
b 04 — 1 5 SZAP
c 0C — 1 5 SZAP
d 14 — 1 5 SZAP
e 1C — 1 5 SZAP
h 24 — 1 5 SZAP
l 2C — 1 5 SZAP
m 34 — 1 10 SZAP
a 3C — 1 5 SZAP

DCR

Decrement register

Mode Opcode Operands Bytes Cycles Flags
b 05 — 1 5 SZAP
c 0D — 1 5 SZAP
d 15 — 1 5 SZAP
e 1D — 1 5 SZAP
h 25 — 1 5 SZAP
l 2D — 1 5 SZAP
m 35 — 1 10 SZAP
a 3D — 1 5 SZAP

INX

Increment register pair

Mode Opcode Operands Bytes Cycles Flags
b 03 — 1 5 —
d 13 — 1 5 —
h 23 — 1 5 —
sp 33 — 1 5 —

DCX

Decrement register pair

Mode Opcode Operands Bytes Cycles Flags
b 0B — 1 5 —
d 1B — 1 5 —
h 2B — 1 5 —
sp 3B — 1 5 —

DAD

Add register pair to HL

Mode Opcode Operands Bytes Cycles Flags
b 09 — 1 10 C
d 19 — 1 10 C
h 29 — 1 10 C
sp 39 — 1 10 C

PUSH

Push register pair

Mode Opcode Operands Bytes Cycles Flags
b C5 — 1 11 —
d D5 — 1 11 —
h E5 — 1 11 —
psw F5 — 1 11 —

POP

Pop register pair

Mode Opcode Operands Bytes Cycles Flags
b C1 — 1 10 —
d D1 — 1 10 —
h E1 — 1 10 —
psw F1 — 1 10 SZAPC

IN

Input from port

Mode Opcode Operands Bytes Cycles Flags
N DB imm8 2 7 —

OUT

Output to port

Mode Opcode Operands Bytes Cycles Flags
N D3 imm8 2 7 —

JMP

Jump

Mode Opcode Operands Bytes Cycles Flags
NN C3 addr16 3 10 —

JNZ

Jump if not zero

Mode Opcode Operands Bytes Cycles Flags
NN C2 addr16 3 10 —

JZ

Jump if zero

Mode Opcode Operands Bytes Cycles Flags
NN CA addr16 3 10 —

JNC

Jump if no carry

Mode Opcode Operands Bytes Cycles Flags
NN D2 addr16 3 10 —

JC

Jump if carry

Mode Opcode Operands Bytes Cycles Flags
NN DA addr16 3 10 —

JPO

Jump if parity odd

Mode Opcode Operands Bytes Cycles Flags
NN E2 addr16 3 10 —

JPE

Jump if parity even

Mode Opcode Operands Bytes Cycles Flags
NN EA addr16 3 10 —

JP

Jump if positive

Mode Opcode Operands Bytes Cycles Flags
NN F2 addr16 3 10 —

JM

Jump if minus

Mode Opcode Operands Bytes Cycles Flags
NN FA addr16 3 10 —

CALL

Call

Mode Opcode Operands Bytes Cycles Flags
NN CD addr16 3 10 —

CNZ

Call if not zero

Mode Opcode Operands Bytes Cycles Flags
NN C4 addr16 3 10 —

CZ

Call if zero

Mode Opcode Operands Bytes Cycles Flags
NN CC addr16 3 10 —

CNC

Call if no carry

Mode Opcode Operands Bytes Cycles Flags
NN D4 addr16 3 10 —

CC

Call if carry

Mode Opcode Operands Bytes Cycles Flags
NN DC addr16 3 10 —

CPO

Call if parity odd

Mode Opcode Operands Bytes Cycles Flags
NN E4 addr16 3 10 —

CPE

Call if parity even

Mode Opcode Operands Bytes Cycles Flags
NN EC addr16 3 10 —

CP

Call if positive

Mode Opcode Operands Bytes Cycles Flags
NN F4 addr16 3 10 —

CM

Call if minus

Mode Opcode Operands Bytes Cycles Flags
NN FC addr16 3 10 —

RET

Return

Mode Opcode Operands Bytes Cycles Flags
C9 — 1 4 —

RNZ

Return if not zero

Mode Opcode Operands Bytes Cycles Flags
C0 — 1 4 —

RZ

Return if zero

Mode Opcode Operands Bytes Cycles Flags
C8 — 1 4 —

RNC

Return if no carry

Mode Opcode Operands Bytes Cycles Flags
D0 — 1 4 —

RC

Return if carry

Mode Opcode Operands Bytes Cycles Flags
D8 — 1 4 —

RPO

Return if parity odd

Mode Opcode Operands Bytes Cycles Flags
E0 — 1 4 —

RPE

Return if parity even

Mode Opcode Operands Bytes Cycles Flags
E8 — 1 4 —

RP

Return if positive

Mode Opcode Operands Bytes Cycles Flags
F0 — 1 4 —

RM

Return if minus

Mode Opcode Operands Bytes Cycles Flags
F8 — 1 4 —

RST

Restart

Mode Opcode Operands Bytes Cycles Flags
0 C7 — 1 11 —
1 CF — 1 11 —
2 D7 — 1 11 —
3 DF — 1 11 —
4 E7 — 1 11 —
5 EF — 1 11 —
6 F7 — 1 11 —
7 FF — 1 11 —

Machines

MITS Altair 8800, IMSAI 8080

Sources

Encodings on this page were taken from:

  • 8080/8085 Software Design, Book 2 — Intel
  • 8085AH Data Sheet — Intel