Reference
Fairchild F8 (3850)
47 mnemonics, 253 encoded forms, operands big-endian. Generated from crates/isa/src/f8.rs.
Cycle counts show the base cost; +p is an extra cycle when an
indexed access crosses a page boundary, +t when a branch is taken.
LR
Load register
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| a,ku | 00 |
— | 1 | 1 | — |
| a,kl | 01 |
— | 1 | 1 | — |
| a,qu | 02 |
— | 1 | 1 | — |
| a,ql | 03 |
— | 1 | 1 | — |
| ku,a | 04 |
— | 1 | 1 | — |
| kl,a | 05 |
— | 1 | 1 | — |
| qu,a | 06 |
— | 1 | 1 | — |
| ql,a | 07 |
— | 1 | 1 | — |
| k,p | 08 |
— | 1 | 1 | — |
| p,k | 09 |
— | 1 | 1 | — |
| a,is | 0A |
— | 1 | 1 | — |
| is,a | 0B |
— | 1 | 1 | — |
| p0,q | 0D |
— | 1 | 1 | — |
| q,dc | 0E |
— | 1 | 1 | — |
| dc,q | 0F |
— | 1 | 1 | — |
| dc,h | 10 |
— | 1 | 1 | — |
| h,dc | 11 |
— | 1 | 1 | — |
| w,j | 1D |
— | 1 | 1 | — |
| j,w | 1E |
— | 1 | 1 | — |
LR
Load A from scratchpad register
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| a,0 | 40 |
— | 1 | 1 | — |
| a,1 | 41 |
— | 1 | 1 | — |
| a,2 | 42 |
— | 1 | 1 | — |
| a,3 | 43 |
— | 1 | 1 | — |
| a,4 | 44 |
— | 1 | 1 | — |
| a,5 | 45 |
— | 1 | 1 | — |
| a,6 | 46 |
— | 1 | 1 | — |
| a,7 | 47 |
— | 1 | 1 | — |
| a,8 | 48 |
— | 1 | 1 | — |
| a,9 | 49 |
— | 1 | 1 | — |
| a,10 | 4A |
— | 1 | 1 | — |
| a,11 | 4B |
— | 1 | 1 | — |
| a,12 | 4C |
— | 1 | 1 | — |
| a,13 | 4D |
— | 1 | 1 | — |
| a,14 | 4E |
— | 1 | 1 | — |
| a,15 | 4F |
— | 1 | 1 | — |
LR
Store A to scratchpad register
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| 0,a | 50 |
— | 1 | 1 | — |
| 1,a | 51 |
— | 1 | 1 | — |
| 2,a | 52 |
— | 1 | 1 | — |
| 3,a | 53 |
— | 1 | 1 | — |
| 4,a | 54 |
— | 1 | 1 | — |
| 5,a | 55 |
— | 1 | 1 | — |
| 6,a | 56 |
— | 1 | 1 | — |
| 7,a | 57 |
— | 1 | 1 | — |
| 8,a | 58 |
— | 1 | 1 | — |
| 9,a | 59 |
— | 1 | 1 | — |
| 10,a | 5A |
— | 1 | 1 | — |
| 11,a | 5B |
— | 1 | 1 | — |
| 12,a | 5C |
— | 1 | 1 | — |
| 13,a | 5D |
— | 1 | 1 | — |
| 14,a | 5E |
— | 1 | 1 | — |
| 15,a | 5F |
— | 1 | 1 | — |
PK
Store PC1 into PC0 via K
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
0C |
— | 1 | 1 | — |
LM
Load A from memory (DC)
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
16 |
— | 1 | 1 | — |
ST
Store A to memory (DC)
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
17 |
— | 1 | 1 | — |
COM
Complement A
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
18 |
— | 1 | 1 | — |
LNK
Add carry link to A
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
19 |
— | 1 | 1 | — |
DI
Disable interrupt
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
1A |
— | 1 | 1 | — |
EI
Enable interrupt
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
1B |
— | 1 | 1 | — |
POP
Pop: PC1 into PC0
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
1C |
— | 1 | 1 | — |
INC
Increment A
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
1F |
— | 1 | 1 | — |
NOP
No operation
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
2B |
— | 1 | 1 | — |
XDC
Exchange DC and DC1
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
2C |
— | 1 | 1 | — |
AM
Add memory to A
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
88 |
— | 1 | 1 | — |
AMD
Decimal add memory to A
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
89 |
— | 1 | 1 | — |
NM
AND memory into A
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
8A |
— | 1 | 1 | — |
OM
OR memory into A
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
8B |
— | 1 | 1 | — |
XM
XOR memory into A
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
8C |
— | 1 | 1 | — |
CM
Compare memory with A
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
8D |
— | 1 | 1 | — |
ADC
Add A to DC
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
8E |
— | 1 | 1 | — |
SR
Shift A right
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| 1 | 12 |
— | 1 | 1 | — |
| 4 | 14 |
— | 1 | 1 | — |
SL
Shift A left
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| 1 | 13 |
— | 1 | 1 | — |
| 4 | 15 |
— | 1 | 1 | — |
LI
Load immediate to A
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| imm | 20 |
imm8 | 2 | 2 | — |
NI
AND immediate
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| imm | 21 |
imm8 | 2 | 2 | — |
OI
OR immediate
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| imm | 22 |
imm8 | 2 | 2 | — |
XI
XOR immediate
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| imm | 23 |
imm8 | 2 | 2 | — |
AI
Add immediate
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| imm | 24 |
imm8 | 2 | 2 | — |
CI
Compare immediate
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| imm | 25 |
imm8 | 2 | 2 | — |
IN
Input port to A
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| port | 26 |
imm8 | 2 | 2 | — |
OUT
Output A to port
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| port | 27 |
imm8 | 2 | 2 | — |
PI
Call subroutine immediate
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| abs | 28 |
addr16 | 3 | 3 | — |
JMP
Jump immediate
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| abs | 29 |
addr16 | 3 | 3 | — |
DCI
Load DC immediate
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| abs | 2A |
addr16 | 3 | 3 | — |
DS
Decrement scratchpad
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| 0 | 30 |
— | 1 | 1 | — |
| 1 | 31 |
— | 1 | 1 | — |
| 2 | 32 |
— | 1 | 1 | — |
| 3 | 33 |
— | 1 | 1 | — |
| 4 | 34 |
— | 1 | 1 | — |
| 5 | 35 |
— | 1 | 1 | — |
| 6 | 36 |
— | 1 | 1 | — |
| 7 | 37 |
— | 1 | 1 | — |
| 8 | 38 |
— | 1 | 1 | — |
| 9 | 39 |
— | 1 | 1 | — |
| 10 | 3A |
— | 1 | 1 | — |
| 11 | 3B |
— | 1 | 1 | — |
| 12 | 3C |
— | 1 | 1 | — |
| 13 | 3D |
— | 1 | 1 | — |
| 14 | 3E |
— | 1 | 1 | — |
| 15 | 3F |
— | 1 | 1 | — |
AS
Add scratchpad to A
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| 0 | C0 |
— | 1 | 1 | — |
| 1 | C1 |
— | 1 | 1 | — |
| 2 | C2 |
— | 1 | 1 | — |
| 3 | C3 |
— | 1 | 1 | — |
| 4 | C4 |
— | 1 | 1 | — |
| 5 | C5 |
— | 1 | 1 | — |
| 6 | C6 |
— | 1 | 1 | — |
| 7 | C7 |
— | 1 | 1 | — |
| 8 | C8 |
— | 1 | 1 | — |
| 9 | C9 |
— | 1 | 1 | — |
| 10 | CA |
— | 1 | 1 | — |
| 11 | CB |
— | 1 | 1 | — |
| 12 | CC |
— | 1 | 1 | — |
| 13 | CD |
— | 1 | 1 | — |
| 14 | CE |
— | 1 | 1 | — |
| 15 | CF |
— | 1 | 1 | — |
ASD
Decimal add scratchpad to A
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| 0 | D0 |
— | 1 | 1 | — |
| 1 | D1 |
— | 1 | 1 | — |
| 2 | D2 |
— | 1 | 1 | — |
| 3 | D3 |
— | 1 | 1 | — |
| 4 | D4 |
— | 1 | 1 | — |
| 5 | D5 |
— | 1 | 1 | — |
| 6 | D6 |
— | 1 | 1 | — |
| 7 | D7 |
— | 1 | 1 | — |
| 8 | D8 |
— | 1 | 1 | — |
| 9 | D9 |
— | 1 | 1 | — |
| 10 | DA |
— | 1 | 1 | — |
| 11 | DB |
— | 1 | 1 | — |
| 12 | DC |
— | 1 | 1 | — |
| 13 | DD |
— | 1 | 1 | — |
| 14 | DE |
— | 1 | 1 | — |
| 15 | DF |
— | 1 | 1 | — |
XS
XOR scratchpad into A
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| 0 | E0 |
— | 1 | 1 | — |
| 1 | E1 |
— | 1 | 1 | — |
| 2 | E2 |
— | 1 | 1 | — |
| 3 | E3 |
— | 1 | 1 | — |
| 4 | E4 |
— | 1 | 1 | — |
| 5 | E5 |
— | 1 | 1 | — |
| 6 | E6 |
— | 1 | 1 | — |
| 7 | E7 |
— | 1 | 1 | — |
| 8 | E8 |
— | 1 | 1 | — |
| 9 | E9 |
— | 1 | 1 | — |
| 10 | EA |
— | 1 | 1 | — |
| 11 | EB |
— | 1 | 1 | — |
| 12 | EC |
— | 1 | 1 | — |
| 13 | ED |
— | 1 | 1 | — |
| 14 | EE |
— | 1 | 1 | — |
| 15 | EF |
— | 1 | 1 | — |
NS
AND scratchpad into A
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| 0 | F0 |
— | 1 | 1 | — |
| 1 | F1 |
— | 1 | 1 | — |
| 2 | F2 |
— | 1 | 1 | — |
| 3 | F3 |
— | 1 | 1 | — |
| 4 | F4 |
— | 1 | 1 | — |
| 5 | F5 |
— | 1 | 1 | — |
| 6 | F6 |
— | 1 | 1 | — |
| 7 | F7 |
— | 1 | 1 | — |
| 8 | F8 |
— | 1 | 1 | — |
| 9 | F9 |
— | 1 | 1 | — |
| 10 | FA |
— | 1 | 1 | — |
| 11 | FB |
— | 1 | 1 | — |
| 12 | FC |
— | 1 | 1 | — |
| 13 | FD |
— | 1 | 1 | — |
| 14 | FE |
— | 1 | 1 | — |
| 15 | FF |
— | 1 | 1 | — |
LISU
Load upper octal digit of ISAR
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| 0 | 60 |
— | 1 | 1 | — |
| 1 | 61 |
— | 1 | 1 | — |
| 2 | 62 |
— | 1 | 1 | — |
| 3 | 63 |
— | 1 | 1 | — |
| 4 | 64 |
— | 1 | 1 | — |
| 5 | 65 |
— | 1 | 1 | — |
| 6 | 66 |
— | 1 | 1 | — |
| 7 | 67 |
— | 1 | 1 | — |
LISL
Load lower octal digit of ISAR
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| 0 | 68 |
— | 1 | 1 | — |
| 1 | 69 |
— | 1 | 1 | — |
| 2 | 6A |
— | 1 | 1 | — |
| 3 | 6B |
— | 1 | 1 | — |
| 4 | 6C |
— | 1 | 1 | — |
| 5 | 6D |
— | 1 | 1 | — |
| 6 | 6E |
— | 1 | 1 | — |
| 7 | 6F |
— | 1 | 1 | — |
LIS
Load 4-bit immediate to A
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| 0 | 70 |
— | 1 | 1 | — |
| 1 | 71 |
— | 1 | 1 | — |
| 2 | 72 |
— | 1 | 1 | — |
| 3 | 73 |
— | 1 | 1 | — |
| 4 | 74 |
— | 1 | 1 | — |
| 5 | 75 |
— | 1 | 1 | — |
| 6 | 76 |
— | 1 | 1 | — |
| 7 | 77 |
— | 1 | 1 | — |
| 8 | 78 |
— | 1 | 1 | — |
| 9 | 79 |
— | 1 | 1 | — |
| 10 | 7A |
— | 1 | 1 | — |
| 11 | 7B |
— | 1 | 1 | — |
| 12 | 7C |
— | 1 | 1 | — |
| 13 | 7D |
— | 1 | 1 | — |
| 14 | 7E |
— | 1 | 1 | — |
| 15 | 7F |
— | 1 | 1 | — |
INS
Input short port to A
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| 0 | A0 |
— | 1 | 1 | — |
| 1 | A1 |
— | 1 | 1 | — |
| 2 | A2 |
— | 1 | 1 | — |
| 3 | A3 |
— | 1 | 1 | — |
| 4 | A4 |
— | 1 | 1 | — |
| 5 | A5 |
— | 1 | 1 | — |
| 6 | A6 |
— | 1 | 1 | — |
| 7 | A7 |
— | 1 | 1 | — |
| 8 | A8 |
— | 1 | 1 | — |
| 9 | A9 |
— | 1 | 1 | — |
| 10 | AA |
— | 1 | 1 | — |
| 11 | AB |
— | 1 | 1 | — |
| 12 | AC |
— | 1 | 1 | — |
| 13 | AD |
— | 1 | 1 | — |
| 14 | AE |
— | 1 | 1 | — |
| 15 | AF |
— | 1 | 1 | — |
OUTS
Output A to short port
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| 0 | B0 |
— | 1 | 1 | — |
| 1 | B1 |
— | 1 | 1 | — |
| 2 | B2 |
— | 1 | 1 | — |
| 3 | B3 |
— | 1 | 1 | — |
| 4 | B4 |
— | 1 | 1 | — |
| 5 | B5 |
— | 1 | 1 | — |
| 6 | B6 |
— | 1 | 1 | — |
| 7 | B7 |
— | 1 | 1 | — |
| 8 | B8 |
— | 1 | 1 | — |
| 9 | B9 |
— | 1 | 1 | — |
| 10 | BA |
— | 1 | 1 | — |
| 11 | BB |
— | 1 | 1 | — |
| 12 | BC |
— | 1 | 1 | — |
| 13 | BD |
— | 1 | 1 | — |
| 14 | BE |
— | 1 | 1 | — |
| 15 | BF |
— | 1 | 1 | — |
BT
Branch on test mask true
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| 0 | 80 |
rel8 | 2 | 2 | — |
| 1 | 81 |
rel8 | 2 | 2 | — |
| 2 | 82 |
rel8 | 2 | 2 | — |
| 3 | 83 |
rel8 | 2 | 2 | — |
| 4 | 84 |
rel8 | 2 | 2 | — |
| 5 | 85 |
rel8 | 2 | 2 | — |
| 6 | 86 |
rel8 | 2 | 2 | — |
| 7 | 87 |
rel8 | 2 | 2 | — |
BF
Branch on test mask false
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| 0 | 90 |
rel8 | 2 | 2 | — |
| 1 | 91 |
rel8 | 2 | 2 | — |
| 2 | 92 |
rel8 | 2 | 2 | — |
| 3 | 93 |
rel8 | 2 | 2 | — |
| 4 | 94 |
rel8 | 2 | 2 | — |
| 5 | 95 |
rel8 | 2 | 2 | — |
| 6 | 96 |
rel8 | 2 | 2 | — |
| 7 | 97 |
rel8 | 2 | 2 | — |
| 8 | 98 |
rel8 | 2 | 2 | — |
| 9 | 99 |
rel8 | 2 | 2 | — |
| 10 | 9A |
rel8 | 2 | 2 | — |
| 11 | 9B |
rel8 | 2 | 2 | — |
| 12 | 9C |
rel8 | 2 | 2 | — |
| 13 | 9D |
rel8 | 2 | 2 | — |
| 14 | 9E |
rel8 | 2 | 2 | — |
| 15 | 9F |
rel8 | 2 | 2 | — |
BR7
Branch if ISAR low octal != 7
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
8F |
rel8 | 2 | 2 | — |
Machines
Sources
Encodings on this page were taken from:
- F8 Guide to Programming, 67095664 — Fairchild