DEC PDP-11

96 instructions, words little-endian. Generated from crates/isa/src/pdp11.rs.

This CPU encodes an instruction as an opcode word whose operand fields are bits inside it, so there is no opcode-then-operands table to give. Each instruction has a base — the opcode word with its operand fields zeroed — and a class saying where those fields sit.

Classes

Class	Encoding	Meaning
`Double`	`base \| src6 << 6 \| dst6`	Two general operands, each a 6-bit mode/register field
`Single`	`base \| dst6`	One general operand
`Branch`	`base \| (offset & 0xFF)`	Signed word-scaled PC offset
`RegSrc`	`base \| reg << 6 \| src6`	Source operand plus a register
`Xor`	`base \| reg << 6 \| dst6`	Register plus a destination operand
`Sob`	`base \| reg << 6 \| offset`	Register plus a backward word offset
`Jsr`	`base \| reg << 6 \| dst6`	Register plus a destination operand
`Trap`	`base \| (n & 0xFF)`	An 8-bit trap number
`Mark`	`base \| (n & 0x3F)`	A 6-bit count
`Spl`	`base \| (n & 7)`	A 3-bit priority level
`Rts`	`base \| reg`	Register in the low three bits
`NoArg`	`base`	No operand, fixed opcode

Instructions

Mnemonic	Base	Class	Summary
MOV	`1000`	`Double`	Move word
CMP	`2000`	`Double`	Compare word
BIT	`3000`	`Double`	Bit test word
BIC	`4000`	`Double`	Bit clear word
BIS	`5000`	`Double`	Bit set word
ADD	`6000`	`Double`	Add word
SUB	`E000`	`Double`	Subtract word
MOVB	`9000`	`Double`	Move byte
CMPB	`A000`	`Double`	Compare byte
BITB	`B000`	`Double`	Bit test byte
BICB	`C000`	`Double`	Bit clear byte
BISB	`D000`	`Double`	Bit set byte
JMP	`0040`	`Single`	Jump
SWAB	`00C0`	`Single`	Swap bytes
CLR	`0A00`	`Single`	Clear word
COM	`0A40`	`Single`	Complement word
INC	`0A80`	`Single`	Increment word
DEC	`0AC0`	`Single`	Decrement word
NEG	`0B00`	`Single`	Negate word
ADC	`0B40`	`Single`	Add carry word
SBC	`0B80`	`Single`	Subtract carry word
TST	`0BC0`	`Single`	Test word
ROR	`0C00`	`Single`	Rotate right word
ROL	`0C40`	`Single`	Rotate left word
ASR	`0C80`	`Single`	Arithmetic shift right word
ASL	`0CC0`	`Single`	Arithmetic shift left word
MFPI	`0D40`	`Single`	Move from previous instruction space
MTPI	`0D80`	`Single`	Move to previous instruction space
SXT	`0DC0`	`Single`	Sign extend
CSM	`0E00`	`Single`	Call to supervisor mode
TSTSET	`0E80`	`Single`	Test and set
WRTLCK	`0EC0`	`Single`	Read-lock, write-unlock
CLRB	`8A00`	`Single`	Clear byte
COMB	`8A40`	`Single`	Complement byte
INCB	`8A80`	`Single`	Increment byte
DECB	`8AC0`	`Single`	Decrement byte
NEGB	`8B00`	`Single`	Negate byte
ADCB	`8B40`	`Single`	Add carry byte
SBCB	`8B80`	`Single`	Subtract carry byte
TSTB	`8BC0`	`Single`	Test byte
RORB	`8C00`	`Single`	Rotate right byte
ROLB	`8C40`	`Single`	Rotate left byte
ASRB	`8C80`	`Single`	Arithmetic shift right byte
ASLB	`8CC0`	`Single`	Arithmetic shift left byte
MTPS	`8D00`	`Single`	Move byte to processor status
MFPD	`8D40`	`Single`	Move from previous data space
MTPD	`8D80`	`Single`	Move to previous data space
MFPS	`8DC0`	`Single`	Move byte from processor status
BR	`0100`	`Branch`	Branch (unconditional)
BNE	`0200`	`Branch`	Branch if not equal
BEQ	`0300`	`Branch`	Branch if equal
BGE	`0400`	`Branch`	Branch if greater or equal
BLT	`0500`	`Branch`	Branch if less than
BGT	`0600`	`Branch`	Branch if greater than
BLE	`0700`	`Branch`	Branch if less or equal
BPL	`8000`	`Branch`	Branch if plus
BMI	`8100`	`Branch`	Branch if minus
BHI	`8200`	`Branch`	Branch if higher
BLOS	`8300`	`Branch`	Branch if lower or same
BVC	`8400`	`Branch`	Branch if overflow clear
BVS	`8500`	`Branch`	Branch if overflow set
BCC	`8600`	`Branch`	Branch if carry clear
BCS	`8700`	`Branch`	Branch if carry set
BHIS	`8600`	`Branch`	Branch if higher or same (= BCC)
BLO	`8700`	`Branch`	Branch if lower (= BCS)
MUL	`7000`	`RegSrc`	Multiply
DIV	`7200`	`RegSrc`	Divide
ASH	`7400`	`RegSrc`	Arithmetic shift
ASHC	`7600`	`RegSrc`	Arithmetic shift combined
XOR	`7800`	`Xor`	Exclusive or
SOB	`7E00`	`Sob`	Subtract one and branch
JSR	`0800`	`Jsr`	Jump to subroutine
EMT	`8800`	`Trap`	Emulator trap
TRAP	`8900`	`Trap`	Trap
MARK	`0D00`	`Mark`	Mark (stack cleanup)
SPL	`0098`	`Spl`	Set priority level
RTS	`0080`	`Rts`	Return from subroutine
HALT	`0000`	`NoArg`	Halt
WAIT	`0001`	`NoArg`	Wait for interrupt
RTI	`0002`	`NoArg`	Return from interrupt
BPT	`0003`	`NoArg`	Breakpoint trap
IOT	`0004`	`NoArg`	I/O trap
RESET	`0005`	`NoArg`	Reset external bus
RTT	`0006`	`NoArg`	Return from interrupt (inhibit T)
MFPT	`0007`	`NoArg`	Move from processor type
NOP	`00A0`	`NoArg`	No operation
CLC	`00A1`	`NoArg`	Clear C
CLV	`00A2`	`NoArg`	Clear V
CLZ	`00A4`	`NoArg`	Clear Z
CLN	`00A8`	`NoArg`	Clear N
CCC	`00AF`	`NoArg`	Clear all condition codes
SEC	`00B1`	`NoArg`	Set C
SEV	`00B2`	`NoArg`	Set V
SEZ	`00B4`	`NoArg`	Set Z
SEN	`00B8`	`NoArg`	Set N
SCC	`00BF`	`NoArg`	Set all condition codes

Machines

DEC PDP-11

Sources

Encodings on this page were taken from:

PDP-11 Processor Handbook, EB-19402-20 — Digital Equipment Corporation, 1981