Reference

Texas Instruments TMS7000

63 mnemonics, 203 encoded forms, operands big-endian. Generated from crates/isa/src/tms7000.rs.

Cycle counts show the base cost; +p is an extra cycle when an indexed access crosses a page boundary, +t when a branch is taken.

MOV

Move

Mode Opcode Operands Bytes Cycles Flags
rn,a 12 imm8 2 0
%n,a 22 imm8 2 0
rn,b 32 imm8 2 0
rn,rn 42 imm8, imm8 3 0
%n,b 52 imm8 2 0
b,a 62 1 0
%n,rn 72 imm8, imm8 3 0

AND

Logical AND

Mode Opcode Operands Bytes Cycles Flags
rn,a 13 imm8 2 0
%n,a 23 imm8 2 0
rn,b 33 imm8 2 0
rn,rn 43 imm8, imm8 3 0
%n,b 53 imm8 2 0
b,a 63 1 0
%n,rn 73 imm8, imm8 3 0

OR

Logical OR

Mode Opcode Operands Bytes Cycles Flags
rn,a 14 imm8 2 0
%n,a 24 imm8 2 0
rn,b 34 imm8 2 0
rn,rn 44 imm8, imm8 3 0
%n,b 54 imm8 2 0
b,a 64 1 0
%n,rn 74 imm8, imm8 3 0

XOR

Logical XOR

Mode Opcode Operands Bytes Cycles Flags
rn,a 15 imm8 2 0
%n,a 25 imm8 2 0
rn,b 35 imm8 2 0
rn,rn 45 imm8, imm8 3 0
%n,b 55 imm8 2 0
b,a 65 1 0
%n,rn 75 imm8, imm8 3 0

BTJO

Bit test and jump if one

Mode Opcode Operands Bytes Cycles Flags
rn,a 16 imm8, rel8 3 0
%n,a 26 imm8, rel8 3 0
rn,b 36 imm8, rel8 3 0
rn,rn 46 imm8, imm8, rel8 4 0
%n,b 56 imm8, rel8 3 0
b,a 66 rel8 2 0
%n,rn 76 imm8, imm8, rel8 4 0

BTJZ

Bit test and jump if zero

Mode Opcode Operands Bytes Cycles Flags
rn,a 17 imm8, rel8 3 0
%n,a 27 imm8, rel8 3 0
rn,b 37 imm8, rel8 3 0
rn,rn 47 imm8, imm8, rel8 4 0
%n,b 57 imm8, rel8 3 0
b,a 67 rel8 2 0
%n,rn 77 imm8, imm8, rel8 4 0

ADD

Add

Mode Opcode Operands Bytes Cycles Flags
rn,a 18 imm8 2 0
%n,a 28 imm8 2 0
rn,b 38 imm8 2 0
rn,rn 48 imm8, imm8 3 0
%n,b 58 imm8 2 0
b,a 68 1 0
%n,rn 78 imm8, imm8 3 0

ADC

Add with carry

Mode Opcode Operands Bytes Cycles Flags
rn,a 19 imm8 2 0
%n,a 29 imm8 2 0
rn,b 39 imm8 2 0
rn,rn 49 imm8, imm8 3 0
%n,b 59 imm8 2 0
b,a 69 1 0
%n,rn 79 imm8, imm8 3 0

SUB

Subtract

Mode Opcode Operands Bytes Cycles Flags
rn,a 1A imm8 2 0
%n,a 2A imm8 2 0
rn,b 3A imm8 2 0
rn,rn 4A imm8, imm8 3 0
%n,b 5A imm8 2 0
b,a 6A 1 0
%n,rn 7A imm8, imm8 3 0

SBB

Subtract with borrow

Mode Opcode Operands Bytes Cycles Flags
rn,a 1B imm8 2 0
%n,a 2B imm8 2 0
rn,b 3B imm8 2 0
rn,rn 4B imm8, imm8 3 0
%n,b 5B imm8 2 0
b,a 6B 1 0
%n,rn 7B imm8, imm8 3 0

MPY

Multiply

Mode Opcode Operands Bytes Cycles Flags
rn,a 1C imm8 2 0
%n,a 2C imm8 2 0
rn,b 3C imm8 2 0
rn,rn 4C imm8, imm8 3 0
%n,b 5C imm8 2 0
b,a 6C 1 0
%n,rn 7C imm8, imm8 3 0

CMP

Compare

Mode Opcode Operands Bytes Cycles Flags
rn,a 1D imm8 2 0
%n,a 2D imm8 2 0
rn,b 3D imm8 2 0
rn,rn 4D imm8, imm8 3 0
%n,b 5D imm8 2 0
b,a 6D 1 0
%n,rn 7D imm8, imm8 3 0

DAC

Decimal add with carry

Mode Opcode Operands Bytes Cycles Flags
rn,a 1E imm8 2 0
%n,a 2E imm8 2 0
rn,b 3E imm8 2 0
rn,rn 4E imm8, imm8 3 0
%n,b 5E imm8 2 0
b,a 6E 1 0
%n,rn 7E imm8, imm8 3 0

DSB

Decimal subtract with borrow

Mode Opcode Operands Bytes Cycles Flags
rn,a 1F imm8 2 0
%n,a 2F imm8 2 0
rn,b 3F imm8 2 0
rn,rn 4F imm8, imm8 3 0
%n,b 5F imm8 2 0
b,a 6F 1 0
%n,rn 7F imm8, imm8 3 0

MOV

Move (A/B source)

Mode Opcode Operands Bytes Cycles Flags
a,b C0 1 0
a,rn D0 imm8 2 0
b,rn D1 imm8 2 0

MOVP

Move to/from peripheral

Mode Opcode Operands Bytes Cycles Flags
pn,a 80 imm8 2 0
pn,b 91 imm8 2 0
a,pn 82 imm8 2 0
b,pn 92 imm8 2 0
%n,pn A2 imm8, imm8 3 0

ANDP

AND with peripheral

Mode Opcode Operands Bytes Cycles Flags
a,pn 83 imm8 2 0
b,pn 93 imm8 2 0
%n,pn A3 imm8, imm8 3 0

ORP

OR with peripheral

Mode Opcode Operands Bytes Cycles Flags
a,pn 84 imm8 2 0
b,pn 94 imm8 2 0
%n,pn A4 imm8, imm8 3 0

XORP

XOR with peripheral

Mode Opcode Operands Bytes Cycles Flags
a,pn 85 imm8 2 0
b,pn 95 imm8 2 0
%n,pn A5 imm8, imm8 3 0

BTJOP

Bit test peripheral and jump if one

Mode Opcode Operands Bytes Cycles Flags
a,pn 86 imm8, rel8 3 0
b,pn 96 imm8, rel8 3 0
%n,pn A6 imm8, imm8, rel8 4 0

BTJZP

Bit test peripheral and jump if zero

Mode Opcode Operands Bytes Cycles Flags
a,pn 87 imm8, rel8 3 0
b,pn 97 imm8, rel8 3 0
%n,pn A7 imm8, imm8, rel8 4 0

LDA

Load A

Mode Opcode Operands Bytes Cycles Flags
@ 8A addr16 3 0
* 9A imm8 2 0
@(b) AA addr16 3 0

STA

Store A

Mode Opcode Operands Bytes Cycles Flags
@ 8B addr16 3 0
* 9B imm8 2 0
@(b) AB addr16 3 0

BR

Branch

Mode Opcode Operands Bytes Cycles Flags
@ 8C addr16 3 0
* 9C imm8 2 0
@(b) AC addr16 3 0

CMPA

Compare A

Mode Opcode Operands Bytes Cycles Flags
@ 8D addr16 3 0
* 9D imm8 2 0
@(b) AD addr16 3 0

CALL

Call

Mode Opcode Operands Bytes Cycles Flags
@ 8E addr16 3 0
* 9E imm8 2 0
@(b) AE addr16 3 0

MOVD

Move double (16-bit)

Mode Opcode Operands Bytes Cycles Flags
%n,rn 88 addr16, imm8 4 0
rn,rn 98 imm8, imm8 3 0
%n(b),rn A8 addr16, imm8 4 0

DEC

Decrement

Mode Opcode Operands Bytes Cycles Flags
a B2 1 0
b C2 1 0
rn D2 imm8 2 0

INC

Increment

Mode Opcode Operands Bytes Cycles Flags
a B3 1 0
b C3 1 0
rn D3 imm8 2 0

INV

Invert

Mode Opcode Operands Bytes Cycles Flags
a B4 1 0
b C4 1 0
rn D4 imm8 2 0

CLR

Clear

Mode Opcode Operands Bytes Cycles Flags
a B5 1 0
b C5 1 0
rn D5 imm8 2 0

XCHB

Exchange with B

Mode Opcode Operands Bytes Cycles Flags
a B6 1 0
b C6 1 0
rn D6 imm8 2 0

SWAP

Swap nibbles

Mode Opcode Operands Bytes Cycles Flags
a B7 1 0
b C7 1 0
rn D7 imm8 2 0

PUSH

Push

Mode Opcode Operands Bytes Cycles Flags
a B8 1 0
b C8 1 0
rn D8 imm8 2 0

POP

Pop

Mode Opcode Operands Bytes Cycles Flags
a B9 1 0
b C9 1 0
rn D9 imm8 2 0

DECD

Decrement double

Mode Opcode Operands Bytes Cycles Flags
a BB 1 0
b CB 1 0
rn DB imm8 2 0

RR

Rotate right

Mode Opcode Operands Bytes Cycles Flags
a BC 1 0
b CC 1 0
rn DC imm8 2 0

RRC

Rotate right through carry

Mode Opcode Operands Bytes Cycles Flags
a BD 1 0
b CD 1 0
rn DD imm8 2 0

RL

Rotate left

Mode Opcode Operands Bytes Cycles Flags
a BE 1 0
b CE 1 0
rn DE imm8 2 0

RLC

Rotate left through carry

Mode Opcode Operands Bytes Cycles Flags
a BF 1 0
b CF 1 0
rn DF imm8 2 0

DJNZ

Decrement and jump if not zero

Mode Opcode Operands Bytes Cycles Flags
a BA rel8 2 0
b CA rel8 2 0
rn DA imm8, rel8 3 0

TSTA

Test A

Mode Opcode Operands Bytes Cycles Flags
B0 1 0

TSTB

Test B

Mode Opcode Operands Bytes Cycles Flags
C1 1 0

PUSH

Push status

Mode Opcode Operands Bytes Cycles Flags
st 0E 1 0

POP

Pop status

Mode Opcode Operands Bytes Cycles Flags
st 08 1 0

JMP

Jump unconditional

Mode Opcode Operands Bytes Cycles Flags
E0 rel8 2 0

JN

Jump if negative

Mode Opcode Operands Bytes Cycles Flags
E1 rel8 2 0

JZ

Jump if zero

Mode Opcode Operands Bytes Cycles Flags
E2 rel8 2 0

JC

Jump if carry

Mode Opcode Operands Bytes Cycles Flags
E3 rel8 2 0

JP

Jump if positive

Mode Opcode Operands Bytes Cycles Flags
E4 rel8 2 0

JPZ

Jump if positive or zero

Mode Opcode Operands Bytes Cycles Flags
E5 rel8 2 0

JNZ

Jump if not zero

Mode Opcode Operands Bytes Cycles Flags
E6 rel8 2 0

JNC

Jump if no carry

Mode Opcode Operands Bytes Cycles Flags
E7 rel8 2 0

NOP

No operation

Mode Opcode Operands Bytes Cycles Flags
00 1 0

IDLE

Idle

Mode Opcode Operands Bytes Cycles Flags
01 1 0

EINT

Enable interrupts

Mode Opcode Operands Bytes Cycles Flags
05 1 0

DINT

Disable interrupts

Mode Opcode Operands Bytes Cycles Flags
06 1 0

SETC

Set carry

Mode Opcode Operands Bytes Cycles Flags
07 1 0

STSP

Store stack pointer

Mode Opcode Operands Bytes Cycles Flags
09 1 0

RETS

Return from subroutine

Mode Opcode Operands Bytes Cycles Flags
0A 1 0

RETI

Return from interrupt

Mode Opcode Operands Bytes Cycles Flags
0B 1 0

LDSP

Load stack pointer

Mode Opcode Operands Bytes Cycles Flags
0D 1 0

CLRC

Clear carry (= TSTA)

Mode Opcode Operands Bytes Cycles Flags
B0 1 0

Sources

Encodings on this page were taken from:

  • TMS7000 Assembly Language Programmer’s Guide — Texas Instruments