Reference

Motorola 6809

123 mnemonics, operands big-endian. Generated from crates/isa/src/mos6809.rs.

The 6809’s indexed mode computes its own length: a postbyte selects the indexing form, and how many bytes follow depends on which form. So the tables below give the opcode for each addressing mode an instruction supports, and the operand that follows is whatever the mode calls for.

Instructions are grouped by operand shape, which is the distinction this CPU’s specification draws.

Register and memory

Each supports some subset of the four standard modes; a blank cell means the mode does not exist for that instruction. Width is the immediate’s size in bytes.

Mnemonic Immediate Direct Indexed Extended Width Summary
lda 86 96 A6 B6 1 Load accumulator A
ldb C6 D6 E6 F6 1 Load accumulator B
sta 97 A7 B7 1 Store accumulator A
stb D7 E7 F7 1 Store accumulator B
ldd CC DC EC FC 2 Load D
std DD ED FD 2 Store D
ldx 8E 9E AE BE 2 Load index register X
stx 9F AF BF 2 Store index register X
ldu CE DE EE FE 2 Load user stack pointer
stu DF EF FF 2 Store user stack pointer
ldy 10 8E 10 9E 10 AE 10 BE 2 Load index register Y
sty 10 9F 10 AF 10 BF 2 Store index register Y
lds 10 CE 10 DE 10 EE 10 FE 2 Load hardware stack pointer
sts 10 DF 10 EF 10 FF 2 Store hardware stack pointer
adda 8B 9B AB BB 1 Add to accumulator A
addb CB DB EB FB 1 Add to accumulator B
adca 89 99 A9 B9 1 Add with carry to accumulator A
adcb C9 D9 E9 F9 1 Add with carry to accumulator B
addd C3 D3 E3 F3 2 Add to D
suba 80 90 A0 B0 1 Subtract from accumulator A
subb C0 D0 E0 F0 1 Subtract from accumulator B
sbca 82 92 A2 B2 1 Subtract with carry from accumulator A
sbcb C2 D2 E2 F2 1 Subtract with carry from accumulator B
subd 83 93 A3 B3 2 Subtract from D
cmpa 81 91 A1 B1 1 Compare accumulator A
cmpb C1 D1 E1 F1 1 Compare accumulator B
cmpx 8C 9C AC BC 2 Compare index register X
cmpd 10 83 10 93 10 A3 10 B3 2 Compare D
cmpy 10 8C 10 9C 10 AC 10 BC 2 Compare index register Y
cmpu 11 83 11 93 11 A3 11 B3 2 Compare user stack pointer
cmps 11 8C 11 9C 11 AC 11 BC 2 Compare hardware stack pointer
anda 84 94 A4 B4 1 Logical AND with accumulator A
andb C4 D4 E4 F4 1 Logical AND with accumulator B
bita 85 95 A5 B5 1 Bit test accumulator A
bitb C5 D5 E5 F5 1 Bit test accumulator B
ora 8A 9A AA BA 1 Logical OR with accumulator A
orb CA DA EA FA 1 Logical OR with accumulator B
eora 88 98 A8 B8 1 Exclusive OR with accumulator A
eorb C8 D8 E8 F8 1 Exclusive OR with accumulator B
andcc 1C 1 AND the condition-code register with an immediate
orcc 1A 1 OR the condition-code register with an immediate
cwai 3C 1 AND condition codes, stack the machine state, wait for interrupt
clr 0F 6F 7F 1 Clear memory
inc 0C 6C 7C 1 Increment memory
dec 0A 6A 7A 1 Decrement memory
tst 0D 6D 7D 1 Test memory
com 03 63 73 1 Complement memory
neg 00 60 70 1 Negate memory
lsr 04 64 74 1 Logical shift right
ror 06 66 76 1 Rotate right through carry
asr 07 67 77 1 Arithmetic shift right
asl 08 68 78 1 Arithmetic shift left
lsl 08 68 78 1 Logical shift left (the same opcode as ASL)
rol 09 69 79 1 Rotate left through carry
jmp 0E 6E 7E 0 Jump
jsr 9D AD BD 0 Jump to subroutine
leax 30 0 Load effective address into X
leay 31 0 Load effective address into Y
leau 33 0 Load effective address into U
leas 32 0 Load effective address into S

Inherent

No operand — the opcode is the whole instruction.

Mnemonic Opcode Summary
nop 12 No operation
sync 13 Synchronise to interrupt
rts 39 Return from subroutine
rti 3B Return from interrupt
swi 3F Software interrupt
swi2 10 3F Software interrupt 2
swi3 11 3F Software interrupt 3
abx 3A Add B to X, unsigned
mul 3D Multiply A by B, unsigned, into D
sex 1D Sign-extend B into A
daa 19 Decimal adjust A after a BCD add
clra 4F Clear accumulator A
clrb 5F Clear accumulator B
nega 40 Negate accumulator A
negb 50 Negate accumulator B
coma 43 Complement accumulator A
comb 53 Complement accumulator B
inca 4C Increment accumulator A
incb 5C Increment accumulator B
deca 4A Decrement accumulator A
decb 5A Decrement accumulator B
tsta 4D Test accumulator A
tstb 5D Test accumulator B
lsra 44 Logical shift right accumulator A
lsrb 54 Logical shift right accumulator B
rora 46 Rotate accumulator A right through carry
rorb 56 Rotate accumulator B right through carry
asra 47 Arithmetic shift right accumulator A
asrb 57 Arithmetic shift right accumulator B
asla 48 Arithmetic shift left accumulator A
aslb 58 Arithmetic shift left accumulator B
lsla 48 Logical shift left accumulator A
lslb 58 Logical shift left accumulator B
rola 49 Rotate accumulator A left through carry
rolb 59 Rotate accumulator B left through carry
reset 3E Reset (undocumented, input only)
rhf 14 Halt and catch fire (undocumented, input only)
hcf 14 Halt and catch fire (undocumented, input only)

Branches

Every branch has a short form with an 8-bit displacement and a long form with a 16-bit one. The assembler picks by range unless the source forces a spelling.

Mnemonic Short Long Summary
bra 20 16 Branch always
brn 21 10 21 Branch never
bhi 22 10 22 Branch if higher
bls 23 10 23 Branch if lower or same
bcc 24 10 24 Branch if carry clear
bhs 24 10 24 Branch if higher or same
bcs 25 10 25 Branch if carry set
blo 25 10 25 Branch if lower
bne 26 10 26 Branch if not equal
beq 27 10 27 Branch if equal
bvc 28 10 28 Branch if overflow clear
bvs 29 10 29 Branch if overflow set
bpl 2A 10 2A Branch if plus
bmi 2B 10 2B Branch if minus
bge 2C 10 2C Branch if greater or equal
blt 2D 10 2D Branch if less than
bgt 2E 10 2E Branch if greater than
ble 2F 10 2F Branch if less or equal
bsr 8D 17 Branch to subroutine

Transfer and exchange

The opcode is followed by a postbyte packing two 4-bit register codes, source in the high nibble. Both registers must be the same width.

Mnemonic Opcode Summary
tfr 1F Transfer one register to another
exg 1E Exchange two registers

Stack

The opcode is followed by a one-byte register mask — PC U/S Y X DP B A CC, high bit first. Registers push in the order CC, A, B, DP, X, Y, U/S, PC and pull in reverse.

Mnemonic Opcode Stack Summary
pshs 34 S Push registers onto the hardware stack
puls 35 S Pull registers from the hardware stack
pshu 36 U Push registers onto the user stack
pulu 37 U Pull registers from the user stack

Machines

Dragon 32/64, Tandy TRS-80

Sources

Encodings on this page were taken from:

  • MC6809-MC6809E 8-Bit Microprocessor Programming Manual — Motorola, 1981
  • MC6809E HMOS 8-Bit Microprocessor Data Sheet — Motorola, 1984