Reference

Sharp SM83 (Game Boy)

46 mnemonics, 504 encoded forms, operands little-endian. Generated from crates/isa/src/sm83.rs.

Cycle counts show the base cost; +p is an extra cycle when an indexed access crosses a page boundary, +t when a branch is taken.

NOP

No operation

Mode Opcode Operands Bytes Cycles Flags
00 1 1

STOP

Stop / standby

Mode Opcode Operands Bytes Cycles Flags
10 00 2 1

HALT

Halt CPU

Mode Opcode Operands Bytes Cycles Flags
76 1 1

DI

Disable interrupts

Mode Opcode Operands Bytes Cycles Flags
F3 1 1

EI

Enable interrupts

Mode Opcode Operands Bytes Cycles Flags
FB 1 1

RLCA

Rotate A left

Mode Opcode Operands Bytes Cycles Flags
07 1 1 ZNHC

RRCA

Rotate A right

Mode Opcode Operands Bytes Cycles Flags
0F 1 1 ZNHC

RLA

Rotate A left thru CY

Mode Opcode Operands Bytes Cycles Flags
17 1 1 ZNHC

RRA

Rotate A right thru CY

Mode Opcode Operands Bytes Cycles Flags
1F 1 1 ZNHC

DAA

Decimal adjust A

Mode Opcode Operands Bytes Cycles Flags
27 1 1 ZHC

CPL

Complement A

Mode Opcode Operands Bytes Cycles Flags
2F 1 1 NH

SCF

Set carry flag

Mode Opcode Operands Bytes Cycles Flags
37 1 1 NHC

CCF

Complement carry flag

Mode Opcode Operands Bytes Cycles Flags
3F 1 1 NHC

LD

Load

Mode Opcode Operands Bytes Cycles Flags
b,b 40 1 1
b,c 41 1 1
b,d 42 1 1
b,e 43 1 1
b,h 44 1 1
b,l 45 1 1
b,[hl] 46 1 2
b,a 47 1 1
c,b 48 1 1
c,c 49 1 1
c,d 4A 1 1
c,e 4B 1 1
c,h 4C 1 1
c,l 4D 1 1
c,[hl] 4E 1 2
c,a 4F 1 1
d,b 50 1 1
d,c 51 1 1
d,d 52 1 1
d,e 53 1 1
d,h 54 1 1
d,l 55 1 1
d,[hl] 56 1 2
d,a 57 1 1
e,b 58 1 1
e,c 59 1 1
e,d 5A 1 1
e,e 5B 1 1
e,h 5C 1 1
e,l 5D 1 1
e,[hl] 5E 1 2
e,a 5F 1 1
h,b 60 1 1
h,c 61 1 1
h,d 62 1 1
h,e 63 1 1
h,h 64 1 1
h,l 65 1 1
h,[hl] 66 1 2
h,a 67 1 1
l,b 68 1 1
l,c 69 1 1
l,d 6A 1 1
l,e 6B 1 1
l,h 6C 1 1
l,l 6D 1 1
l,[hl] 6E 1 2
l,a 6F 1 1
[hl],b 70 1 2
[hl],c 71 1 2
[hl],d 72 1 2
[hl],e 73 1 2
[hl],h 74 1 2
[hl],l 75 1 2
[hl],a 77 1 2
a,b 78 1 1
a,c 79 1 1
a,d 7A 1 1
a,e 7B 1 1
a,h 7C 1 1
a,l 7D 1 1
a,[hl] 7E 1 2
a,a 7F 1 1
b,N 06 imm8 2 2
c,N 0E imm8 2 2
d,N 16 imm8 2 2
e,N 1E imm8 2 2
h,N 26 imm8 2 2
l,N 2E imm8 2 2
[hl],N 36 imm8 2 3
a,N 3E imm8 2 2
[bc],a 02 1 2
[de],a 12 1 2
[hl+],a 22 1 2
[hl-],a 32 1 2
a,[bc] 0A 1 2
a,[de] 1A 1 2
a,[hl+] 2A 1 2
a,[hl-] 3A 1 2
[NN],a EA addr16 3 4
a,[NN] FA addr16 3 4
bc,NN 01 addr16 3 3
de,NN 11 addr16 3 3
hl,NN 21 addr16 3 3
sp,NN 31 addr16 3 3
[NN],sp 08 addr16 3 5
sp,hl F9 1 2
hl,sp+D F8 disp8 2 3 ZNHC

LDI

Load and increment HL

Mode Opcode Operands Bytes Cycles Flags
[hl],a 22 1 2
a,[hl] 2A 1 2

LDD

Load and decrement HL

Mode Opcode Operands Bytes Cycles Flags
[hl],a 32 1 2
a,[hl] 3A 1 2

LDH

Load high page

Mode Opcode Operands Bytes Cycles Flags
[$ff00+N],a E0 imm8 2 3
a,[$ff00+N] F0 imm8 2 3
[c],a E2 1 2
a,[c] F2 1 2

ADD

Add

Mode Opcode Operands Bytes Cycles Flags
a,b 80 1 1 ZNHC
a,c 81 1 1 ZNHC
a,d 82 1 1 ZNHC
a,e 83 1 1 ZNHC
a,h 84 1 1 ZNHC
a,l 85 1 1 ZNHC
a,[hl] 86 1 2 ZNHC
a,a 87 1 1 ZNHC
a,N C6 imm8 2 2 ZNHC
hl,bc 09 1 2 NHC
hl,de 19 1 2 NHC
hl,hl 29 1 2 NHC
hl,sp 39 1 2 NHC
sp,D E8 disp8 2 4 ZNHC

ADC

Add with carry

Mode Opcode Operands Bytes Cycles Flags
a,b 88 1 1 ZNHC
a,c 89 1 1 ZNHC
a,d 8A 1 1 ZNHC
a,e 8B 1 1 ZNHC
a,h 8C 1 1 ZNHC
a,l 8D 1 1 ZNHC
a,[hl] 8E 1 2 ZNHC
a,a 8F 1 1 ZNHC
a,N CE imm8 2 2 ZNHC

SUB

Subtract

Mode Opcode Operands Bytes Cycles Flags
a,b 90 1 1 ZNHC
a,c 91 1 1 ZNHC
a,d 92 1 1 ZNHC
a,e 93 1 1 ZNHC
a,h 94 1 1 ZNHC
a,l 95 1 1 ZNHC
a,[hl] 96 1 2 ZNHC
a,a 97 1 1 ZNHC
a,N D6 imm8 2 2 ZNHC

SBC

Subtract with carry

Mode Opcode Operands Bytes Cycles Flags
a,b 98 1 1 ZNHC
a,c 99 1 1 ZNHC
a,d 9A 1 1 ZNHC
a,e 9B 1 1 ZNHC
a,h 9C 1 1 ZNHC
a,l 9D 1 1 ZNHC
a,[hl] 9E 1 2 ZNHC
a,a 9F 1 1 ZNHC
a,N DE imm8 2 2 ZNHC

AND

Logical AND

Mode Opcode Operands Bytes Cycles Flags
a,b A0 1 1 ZNHC
a,c A1 1 1 ZNHC
a,d A2 1 1 ZNHC
a,e A3 1 1 ZNHC
a,h A4 1 1 ZNHC
a,l A5 1 1 ZNHC
a,[hl] A6 1 2 ZNHC
a,a A7 1 1 ZNHC
a,N E6 imm8 2 2 ZNHC

XOR

Logical XOR

Mode Opcode Operands Bytes Cycles Flags
a,b A8 1 1 ZNHC
a,c A9 1 1 ZNHC
a,d AA 1 1 ZNHC
a,e AB 1 1 ZNHC
a,h AC 1 1 ZNHC
a,l AD 1 1 ZNHC
a,[hl] AE 1 2 ZNHC
a,a AF 1 1 ZNHC
a,N EE imm8 2 2 ZNHC

OR

Logical OR

Mode Opcode Operands Bytes Cycles Flags
a,b B0 1 1 ZNHC
a,c B1 1 1 ZNHC
a,d B2 1 1 ZNHC
a,e B3 1 1 ZNHC
a,h B4 1 1 ZNHC
a,l B5 1 1 ZNHC
a,[hl] B6 1 2 ZNHC
a,a B7 1 1 ZNHC
a,N F6 imm8 2 2 ZNHC

CP

Compare

Mode Opcode Operands Bytes Cycles Flags
a,b B8 1 1 ZNHC
a,c B9 1 1 ZNHC
a,d BA 1 1 ZNHC
a,e BB 1 1 ZNHC
a,h BC 1 1 ZNHC
a,l BD 1 1 ZNHC
a,[hl] BE 1 2 ZNHC
a,a BF 1 1 ZNHC
a,N FE imm8 2 2 ZNHC

INC

Increment

Mode Opcode Operands Bytes Cycles Flags
b 04 1 1 ZNH
c 0C 1 1 ZNH
d 14 1 1 ZNH
e 1C 1 1 ZNH
h 24 1 1 ZNH
l 2C 1 1 ZNH
[hl] 34 1 3 ZNH
a 3C 1 1 ZNH
bc 03 1 2
de 13 1 2
hl 23 1 2
sp 33 1 2

DEC

Decrement

Mode Opcode Operands Bytes Cycles Flags
b 05 1 1 ZNH
c 0D 1 1 ZNH
d 15 1 1 ZNH
e 1D 1 1 ZNH
h 25 1 1 ZNH
l 2D 1 1 ZNH
[hl] 35 1 3 ZNH
a 3D 1 1 ZNH
bc 0B 1 2
de 1B 1 2
hl 2B 1 2
sp 3B 1 2

JP

Jump

Mode Opcode Operands Bytes Cycles Flags
NN C3 addr16 3 4
nz,NN C2 addr16 3 4
z,NN CA addr16 3 4
nc,NN D2 addr16 3 4
c,NN DA addr16 3 4
hl E9 1 1

JR

Relative jump

Mode Opcode Operands Bytes Cycles Flags
E 18 rel8 2 3
nz,E 20 rel8 2 3
z,E 28 rel8 2 3
nc,E 30 rel8 2 3
c,E 38 rel8 2 3

CALL

Call subroutine

Mode Opcode Operands Bytes Cycles Flags
NN CD addr16 3 6
nz,NN C4 addr16 3 6
z,NN CC addr16 3 6
nc,NN D4 addr16 3 6
c,NN DC addr16 3 6

RET

Return

Mode Opcode Operands Bytes Cycles Flags
C9 1 4
nz C0 1 2
z C8 1 2
nc D0 1 2
c D8 1 2

RETI

Return from interrupt

Mode Opcode Operands Bytes Cycles Flags
D9 1 4

RST

Restart

Mode Opcode Operands Bytes Cycles Flags
00 C7 1 4
08 CF 1 4
10 D7 1 4
18 DF 1 4
20 E7 1 4
28 EF 1 4
30 F7 1 4
38 FF 1 4

PUSH

Push

Mode Opcode Operands Bytes Cycles Flags
bc C5 1 4
de D5 1 4
hl E5 1 4
af F5 1 4

POP

Pop

Mode Opcode Operands Bytes Cycles Flags
bc C1 1 3
de D1 1 3
hl E1 1 3
af F1 1 3 ZNHC

RLC

Rotate left

Mode Opcode Operands Bytes Cycles Flags
b CB 00 2 2 ZNHC
c CB 01 2 2 ZNHC
d CB 02 2 2 ZNHC
e CB 03 2 2 ZNHC
h CB 04 2 2 ZNHC
l CB 05 2 2 ZNHC
[hl] CB 06 2 4 ZNHC
a CB 07 2 2 ZNHC

RRC

Rotate right

Mode Opcode Operands Bytes Cycles Flags
b CB 08 2 2 ZNHC
c CB 09 2 2 ZNHC
d CB 0A 2 2 ZNHC
e CB 0B 2 2 ZNHC
h CB 0C 2 2 ZNHC
l CB 0D 2 2 ZNHC
[hl] CB 0E 2 4 ZNHC
a CB 0F 2 2 ZNHC

RL

Rotate left thru CY

Mode Opcode Operands Bytes Cycles Flags
b CB 10 2 2 ZNHC
c CB 11 2 2 ZNHC
d CB 12 2 2 ZNHC
e CB 13 2 2 ZNHC
h CB 14 2 2 ZNHC
l CB 15 2 2 ZNHC
[hl] CB 16 2 4 ZNHC
a CB 17 2 2 ZNHC

RR

Rotate right thru CY

Mode Opcode Operands Bytes Cycles Flags
b CB 18 2 2 ZNHC
c CB 19 2 2 ZNHC
d CB 1A 2 2 ZNHC
e CB 1B 2 2 ZNHC
h CB 1C 2 2 ZNHC
l CB 1D 2 2 ZNHC
[hl] CB 1E 2 4 ZNHC
a CB 1F 2 2 ZNHC

SLA

Shift left arithmetic

Mode Opcode Operands Bytes Cycles Flags
b CB 20 2 2 ZNHC
c CB 21 2 2 ZNHC
d CB 22 2 2 ZNHC
e CB 23 2 2 ZNHC
h CB 24 2 2 ZNHC
l CB 25 2 2 ZNHC
[hl] CB 26 2 4 ZNHC
a CB 27 2 2 ZNHC

SRA

Shift right arithmetic

Mode Opcode Operands Bytes Cycles Flags
b CB 28 2 2 ZNHC
c CB 29 2 2 ZNHC
d CB 2A 2 2 ZNHC
e CB 2B 2 2 ZNHC
h CB 2C 2 2 ZNHC
l CB 2D 2 2 ZNHC
[hl] CB 2E 2 4 ZNHC
a CB 2F 2 2 ZNHC

SWAP

Swap nibbles

Mode Opcode Operands Bytes Cycles Flags
b CB 30 2 2 ZNHC
c CB 31 2 2 ZNHC
d CB 32 2 2 ZNHC
e CB 33 2 2 ZNHC
h CB 34 2 2 ZNHC
l CB 35 2 2 ZNHC
[hl] CB 36 2 4 ZNHC
a CB 37 2 2 ZNHC

SRL

Shift right logical

Mode Opcode Operands Bytes Cycles Flags
b CB 38 2 2 ZNHC
c CB 39 2 2 ZNHC
d CB 3A 2 2 ZNHC
e CB 3B 2 2 ZNHC
h CB 3C 2 2 ZNHC
l CB 3D 2 2 ZNHC
[hl] CB 3E 2 4 ZNHC
a CB 3F 2 2 ZNHC

BIT

Test bit

Mode Opcode Operands Bytes Cycles Flags
0,b CB 40 2 2 ZNH
0,c CB 41 2 2 ZNH
0,d CB 42 2 2 ZNH
0,e CB 43 2 2 ZNH
0,h CB 44 2 2 ZNH
0,l CB 45 2 2 ZNH
0,[hl] CB 46 2 3 ZNH
0,a CB 47 2 2 ZNH
1,b CB 48 2 2 ZNH
1,c CB 49 2 2 ZNH
1,d CB 4A 2 2 ZNH
1,e CB 4B 2 2 ZNH
1,h CB 4C 2 2 ZNH
1,l CB 4D 2 2 ZNH
1,[hl] CB 4E 2 3 ZNH
1,a CB 4F 2 2 ZNH
2,b CB 50 2 2 ZNH
2,c CB 51 2 2 ZNH
2,d CB 52 2 2 ZNH
2,e CB 53 2 2 ZNH
2,h CB 54 2 2 ZNH
2,l CB 55 2 2 ZNH
2,[hl] CB 56 2 3 ZNH
2,a CB 57 2 2 ZNH
3,b CB 58 2 2 ZNH
3,c CB 59 2 2 ZNH
3,d CB 5A 2 2 ZNH
3,e CB 5B 2 2 ZNH
3,h CB 5C 2 2 ZNH
3,l CB 5D 2 2 ZNH
3,[hl] CB 5E 2 3 ZNH
3,a CB 5F 2 2 ZNH
4,b CB 60 2 2 ZNH
4,c CB 61 2 2 ZNH
4,d CB 62 2 2 ZNH
4,e CB 63 2 2 ZNH
4,h CB 64 2 2 ZNH
4,l CB 65 2 2 ZNH
4,[hl] CB 66 2 3 ZNH
4,a CB 67 2 2 ZNH
5,b CB 68 2 2 ZNH
5,c CB 69 2 2 ZNH
5,d CB 6A 2 2 ZNH
5,e CB 6B 2 2 ZNH
5,h CB 6C 2 2 ZNH
5,l CB 6D 2 2 ZNH
5,[hl] CB 6E 2 3 ZNH
5,a CB 6F 2 2 ZNH
6,b CB 70 2 2 ZNH
6,c CB 71 2 2 ZNH
6,d CB 72 2 2 ZNH
6,e CB 73 2 2 ZNH
6,h CB 74 2 2 ZNH
6,l CB 75 2 2 ZNH
6,[hl] CB 76 2 3 ZNH
6,a CB 77 2 2 ZNH
7,b CB 78 2 2 ZNH
7,c CB 79 2 2 ZNH
7,d CB 7A 2 2 ZNH
7,e CB 7B 2 2 ZNH
7,h CB 7C 2 2 ZNH
7,l CB 7D 2 2 ZNH
7,[hl] CB 7E 2 3 ZNH
7,a CB 7F 2 2 ZNH

RES

Reset bit

Mode Opcode Operands Bytes Cycles Flags
0,b CB 80 2 2
0,c CB 81 2 2
0,d CB 82 2 2
0,e CB 83 2 2
0,h CB 84 2 2
0,l CB 85 2 2
0,[hl] CB 86 2 4
0,a CB 87 2 2
1,b CB 88 2 2
1,c CB 89 2 2
1,d CB 8A 2 2
1,e CB 8B 2 2
1,h CB 8C 2 2
1,l CB 8D 2 2
1,[hl] CB 8E 2 4
1,a CB 8F 2 2
2,b CB 90 2 2
2,c CB 91 2 2
2,d CB 92 2 2
2,e CB 93 2 2
2,h CB 94 2 2
2,l CB 95 2 2
2,[hl] CB 96 2 4
2,a CB 97 2 2
3,b CB 98 2 2
3,c CB 99 2 2
3,d CB 9A 2 2
3,e CB 9B 2 2
3,h CB 9C 2 2
3,l CB 9D 2 2
3,[hl] CB 9E 2 4
3,a CB 9F 2 2
4,b CB A0 2 2
4,c CB A1 2 2
4,d CB A2 2 2
4,e CB A3 2 2
4,h CB A4 2 2
4,l CB A5 2 2
4,[hl] CB A6 2 4
4,a CB A7 2 2
5,b CB A8 2 2
5,c CB A9 2 2
5,d CB AA 2 2
5,e CB AB 2 2
5,h CB AC 2 2
5,l CB AD 2 2
5,[hl] CB AE 2 4
5,a CB AF 2 2
6,b CB B0 2 2
6,c CB B1 2 2
6,d CB B2 2 2
6,e CB B3 2 2
6,h CB B4 2 2
6,l CB B5 2 2
6,[hl] CB B6 2 4
6,a CB B7 2 2
7,b CB B8 2 2
7,c CB B9 2 2
7,d CB BA 2 2
7,e CB BB 2 2
7,h CB BC 2 2
7,l CB BD 2 2
7,[hl] CB BE 2 4
7,a CB BF 2 2

SET

Set bit

Mode Opcode Operands Bytes Cycles Flags
0,b CB C0 2 2
0,c CB C1 2 2
0,d CB C2 2 2
0,e CB C3 2 2
0,h CB C4 2 2
0,l CB C5 2 2
0,[hl] CB C6 2 4
0,a CB C7 2 2
1,b CB C8 2 2
1,c CB C9 2 2
1,d CB CA 2 2
1,e CB CB 2 2
1,h CB CC 2 2
1,l CB CD 2 2
1,[hl] CB CE 2 4
1,a CB CF 2 2
2,b CB D0 2 2
2,c CB D1 2 2
2,d CB D2 2 2
2,e CB D3 2 2
2,h CB D4 2 2
2,l CB D5 2 2
2,[hl] CB D6 2 4
2,a CB D7 2 2
3,b CB D8 2 2
3,c CB D9 2 2
3,d CB DA 2 2
3,e CB DB 2 2
3,h CB DC 2 2
3,l CB DD 2 2
3,[hl] CB DE 2 4
3,a CB DF 2 2
4,b CB E0 2 2
4,c CB E1 2 2
4,d CB E2 2 2
4,e CB E3 2 2
4,h CB E4 2 2
4,l CB E5 2 2
4,[hl] CB E6 2 4
4,a CB E7 2 2
5,b CB E8 2 2
5,c CB E9 2 2
5,d CB EA 2 2
5,e CB EB 2 2
5,h CB EC 2 2
5,l CB ED 2 2
5,[hl] CB EE 2 4
5,a CB EF 2 2
6,b CB F0 2 2
6,c CB F1 2 2
6,d CB F2 2 2
6,e CB F3 2 2
6,h CB F4 2 2
6,l CB F5 2 2
6,[hl] CB F6 2 4
6,a CB F7 2 2
7,b CB F8 2 2
7,c CB F9 2 2
7,d CB FA 2 2
7,e CB FB 2 2
7,h CB FC 2 2
7,l CB FD 2 2
7,[hl] CB FE 2 4
7,a CB FF 2 2

Machines

Nintendo Game Boy

Sources

Encodings on this page were taken from:

  • SM83 Programming Manual — Sharp