Reference

TI TMS9900

69 instructions, words big-endian. Generated from crates/isa/src/tms9900.rs.

This CPU encodes an instruction as an opcode word whose operand fields are bits inside it, so there is no opcode-then-operands table to give. Each instruction has a base — the opcode word with its operand fields zeroed — and a class saying where those fields sit.

Classes

Class Encoding Meaning
ImmReg base | W Format VIII — workspace register plus an immediate word
StoreReg base | W Format VIII — store into a workspace register
ImmOnly base Format VIII — an immediate word, no register
Control base Format VII — no operand, fixed opcode
SingleGeneral base | Ts<<4 | S Format VI — one general operand
Shift base | count<<4 | W Format V — workspace register, shift count 0–15
Jump base | (off & 0xFF) Format II jump — word-scaled PC-relative
Cru base | (disp & 0xFF) Format II CRU-bit — signed CRU offset
DualRegDst base | D<<6 | Ts<<4 | S Format III/IX — general source, register destination
Xop base | D<<6 | Ts<<4 | S Format IX XOP — general source, XOP number 0–15
CruMulti base | (count & 0xF)<<6 | Ts<<4 | S Format IV — general source, CRU bit count 1–16
DualGeneral base | Td<<10 | D<<6 | Ts<<4 | S Format I — two general operands

Instructions

Mnemonic Base Class Summary
LI 0200 ImmReg Load immediate
AI 0220 ImmReg Add immediate
ANDI 0240 ImmReg AND immediate
ORI 0260 ImmReg OR immediate
CI 0280 ImmReg Compare immediate
STWP 02A0 StoreReg Store workspace pointer
STST 02C0 StoreReg Store status register
LWPI 02E0 ImmOnly Load workspace pointer immediate
LIMI 0300 ImmOnly Load interrupt mask immediate
IDLE 0340 Control Idle
RSET 0360 Control Reset
RTWP 0380 Control Return with workspace pointer
CKON 03A0 Control Clock on
CKOF 03C0 Control Clock off
LREX 03E0 Control Load or restart execution
BLWP 0400 SingleGeneral Branch and load workspace pointer
B 0440 SingleGeneral Branch
X 0480 SingleGeneral Execute
CLR 04C0 SingleGeneral Clear
NEG 0500 SingleGeneral Negate
INV 0540 SingleGeneral Invert
INC 0580 SingleGeneral Increment
INCT 05C0 SingleGeneral Increment by two
DEC 0600 SingleGeneral Decrement
DECT 0640 SingleGeneral Decrement by two
BL 0680 SingleGeneral Branch and link
SWPB 06C0 SingleGeneral Swap bytes
SETO 0700 SingleGeneral Set to ones
ABS 0740 SingleGeneral Absolute value
SRA 0800 Shift Shift right arithmetic
SRL 0900 Shift Shift right logical
SLA 0A00 Shift Shift left arithmetic
SRC 0B00 Shift Shift right circular
JMP 1000 Jump Jump unconditional
JLT 1100 Jump Jump if less than
JLE 1200 Jump Jump if low or equal
JEQ 1300 Jump Jump if equal
JHE 1400 Jump Jump if high or equal
JGT 1500 Jump Jump if greater than
JNE 1600 Jump Jump if not equal
JNC 1700 Jump Jump if no carry
JOC 1800 Jump Jump on carry
JNO 1900 Jump Jump if no overflow
JL 1A00 Jump Jump if logical low
JH 1B00 Jump Jump if logical high
JOP 1C00 Jump Jump if odd parity
SBO 1D00 Cru Set CRU bit to one
SBZ 1E00 Cru Set CRU bit to zero
TB 1F00 Cru Test CRU bit
COC 2000 DualRegDst Compare ones corresponding
CZC 2400 DualRegDst Compare zeros corresponding
XOR 2800 DualRegDst Exclusive or
XOP 2C00 Xop Extended operation
MPY 3800 DualRegDst Multiply
DIV 3C00 DualRegDst Divide
LDCR 3000 CruMulti Load CRU
STCR 3400 CruMulti Store CRU
SZC 4000 DualGeneral Set zeros corresponding
SZCB 5000 DualGeneral Set zeros corresponding, byte
S 6000 DualGeneral Subtract
SB 7000 DualGeneral Subtract byte
C 8000 DualGeneral Compare
CB 9000 DualGeneral Compare byte
A A000 DualGeneral Add
AB B000 DualGeneral Add byte
MOV C000 DualGeneral Move
MOVB D000 DualGeneral Move byte
SOC E000 DualGeneral Set ones corresponding
SOCB F000 DualGeneral Set ones corresponding, byte

Machines

Texas Instruments TI-99/4A

Sources

Encodings on this page were taken from:

  • TMS9900 Microprocessor Data Manual — Texas Instruments, 1976