Reference
Signetics 2650
71 mnemonics, 245 encoded forms, operands big-endian. Generated from crates/isa/src/s2650.rs.
Cycle counts show the base cost; +p is an extra cycle when an
indexed access crosses a page boundary, +t when a branch is taken.
LODZ
Load register zero
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r1 | 01 |
— | 1 | 2 | — |
| r2 | 02 |
— | 1 | 2 | — |
| r3 | 03 |
— | 1 | 2 | — |
LODI
Load immediate
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r0 | 04 |
imm8 | 2 | 2 | — |
| r1 | 05 |
imm8 | 2 | 2 | — |
| r2 | 06 |
imm8 | 2 | 2 | — |
| r3 | 07 |
imm8 | 2 | 2 | — |
LODR
Load relative
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r0 | 08 |
rel8 | 2 | 3 | — |
| r1 | 09 |
rel8 | 2 | 3 | — |
| r2 | 0A |
rel8 | 2 | 3 | — |
| r3 | 0B |
rel8 | 2 | 3 | — |
LODA
Load absolute
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r0 | 0C |
addr16 | 3 | 4 | — |
| r1 | 0D |
addr16 | 3 | 4 | — |
| r2 | 0E |
addr16 | 3 | 4 | — |
| r3 | 0F |
addr16 | 3 | 4 | — |
STRZ
Store register zero
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r1 | C1 |
— | 1 | 2 | — |
| r2 | C2 |
— | 1 | 2 | — |
| r3 | C3 |
— | 1 | 2 | — |
STRR
Store relative
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r0 | C8 |
rel8 | 2 | 3 | — |
| r1 | C9 |
rel8 | 2 | 3 | — |
| r2 | CA |
rel8 | 2 | 3 | — |
| r3 | CB |
rel8 | 2 | 3 | — |
STRA
Store absolute
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r0 | CC |
addr16 | 3 | 4 | — |
| r1 | CD |
addr16 | 3 | 4 | — |
| r2 | CE |
addr16 | 3 | 4 | — |
| r3 | CF |
addr16 | 3 | 4 | — |
ADDZ
Add to register zero
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r0 | 80 |
— | 1 | 2 | — |
| r1 | 81 |
— | 1 | 2 | — |
| r2 | 82 |
— | 1 | 2 | — |
| r3 | 83 |
— | 1 | 2 | — |
ADDI
Add immediate
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r0 | 84 |
imm8 | 2 | 2 | — |
| r1 | 85 |
imm8 | 2 | 2 | — |
| r2 | 86 |
imm8 | 2 | 2 | — |
| r3 | 87 |
imm8 | 2 | 2 | — |
ADDR
Add relative
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r0 | 88 |
rel8 | 2 | 3 | — |
| r1 | 89 |
rel8 | 2 | 3 | — |
| r2 | 8A |
rel8 | 2 | 3 | — |
| r3 | 8B |
rel8 | 2 | 3 | — |
ADDA
Add absolute
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r0 | 8C |
addr16 | 3 | 4 | — |
| r1 | 8D |
addr16 | 3 | 4 | — |
| r2 | 8E |
addr16 | 3 | 4 | — |
| r3 | 8F |
addr16 | 3 | 4 | — |
SUBZ
Subtract from register zero
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r0 | A0 |
— | 1 | 2 | — |
| r1 | A1 |
— | 1 | 2 | — |
| r2 | A2 |
— | 1 | 2 | — |
| r3 | A3 |
— | 1 | 2 | — |
SUBI
Subtract immediate
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r0 | A4 |
imm8 | 2 | 2 | — |
| r1 | A5 |
imm8 | 2 | 2 | — |
| r2 | A6 |
imm8 | 2 | 2 | — |
| r3 | A7 |
imm8 | 2 | 2 | — |
SUBR
Subtract relative
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r0 | A8 |
rel8 | 2 | 3 | — |
| r1 | A9 |
rel8 | 2 | 3 | — |
| r2 | AA |
rel8 | 2 | 3 | — |
| r3 | AB |
rel8 | 2 | 3 | — |
SUBA
Subtract absolute
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r0 | AC |
addr16 | 3 | 4 | — |
| r1 | AD |
addr16 | 3 | 4 | — |
| r2 | AE |
addr16 | 3 | 4 | — |
| r3 | AF |
addr16 | 3 | 4 | — |
DAR
Decimal adjust register
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r0 | 94 |
— | 1 | 3 | — |
| r1 | 95 |
— | 1 | 3 | — |
| r2 | 96 |
— | 1 | 3 | — |
| r3 | 97 |
— | 1 | 3 | — |
ANDZ
AND to register zero
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r1 | 41 |
— | 1 | 2 | — |
| r2 | 42 |
— | 1 | 2 | — |
| r3 | 43 |
— | 1 | 2 | — |
ANDI
AND immediate
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r0 | 44 |
imm8 | 2 | 2 | — |
| r1 | 45 |
imm8 | 2 | 2 | — |
| r2 | 46 |
imm8 | 2 | 2 | — |
| r3 | 47 |
imm8 | 2 | 2 | — |
ANDR
AND relative
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r0 | 48 |
rel8 | 2 | 3 | — |
| r1 | 49 |
rel8 | 2 | 3 | — |
| r2 | 4A |
rel8 | 2 | 3 | — |
| r3 | 4B |
rel8 | 2 | 3 | — |
ANDA
AND absolute
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r0 | 4C |
addr16 | 3 | 4 | — |
| r1 | 4D |
addr16 | 3 | 4 | — |
| r2 | 4E |
addr16 | 3 | 4 | — |
| r3 | 4F |
addr16 | 3 | 4 | — |
IORZ
Inclusive-OR to register zero
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r0 | 60 |
— | 1 | 2 | — |
| r1 | 61 |
— | 1 | 2 | — |
| r2 | 62 |
— | 1 | 2 | — |
| r3 | 63 |
— | 1 | 2 | — |
IORI
Inclusive-OR immediate
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r0 | 64 |
imm8 | 2 | 2 | — |
| r1 | 65 |
imm8 | 2 | 2 | — |
| r2 | 66 |
imm8 | 2 | 2 | — |
| r3 | 67 |
imm8 | 2 | 2 | — |
IORR
Inclusive-OR relative
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r0 | 68 |
rel8 | 2 | 3 | — |
| r1 | 69 |
rel8 | 2 | 3 | — |
| r2 | 6A |
rel8 | 2 | 3 | — |
| r3 | 6B |
rel8 | 2 | 3 | — |
IORA
Inclusive-OR absolute
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r0 | 6C |
addr16 | 3 | 4 | — |
| r1 | 6D |
addr16 | 3 | 4 | — |
| r2 | 6E |
addr16 | 3 | 4 | — |
| r3 | 6F |
addr16 | 3 | 4 | — |
EORZ
Exclusive-OR to register zero
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r0 | 20 |
— | 1 | 2 | — |
| r1 | 21 |
— | 1 | 2 | — |
| r2 | 22 |
— | 1 | 2 | — |
| r3 | 23 |
— | 1 | 2 | — |
EORI
Exclusive-OR immediate
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r0 | 24 |
imm8 | 2 | 2 | — |
| r1 | 25 |
imm8 | 2 | 2 | — |
| r2 | 26 |
imm8 | 2 | 2 | — |
| r3 | 27 |
imm8 | 2 | 2 | — |
EORR
Exclusive-OR relative
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r0 | 28 |
rel8 | 2 | 3 | — |
| r1 | 29 |
rel8 | 2 | 3 | — |
| r2 | 2A |
rel8 | 2 | 3 | — |
| r3 | 2B |
rel8 | 2 | 3 | — |
EORA
Exclusive-OR absolute
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r0 | 2C |
addr16 | 3 | 4 | — |
| r1 | 2D |
addr16 | 3 | 4 | — |
| r2 | 2E |
addr16 | 3 | 4 | — |
| r3 | 2F |
addr16 | 3 | 4 | — |
COMZ
Compare to register zero
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r0 | E0 |
— | 1 | 2 | — |
| r1 | E1 |
— | 1 | 2 | — |
| r2 | E2 |
— | 1 | 2 | — |
| r3 | E3 |
— | 1 | 2 | — |
COMI
Compare immediate
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r0 | E4 |
imm8 | 2 | 2 | — |
| r1 | E5 |
imm8 | 2 | 2 | — |
| r2 | E6 |
imm8 | 2 | 2 | — |
| r3 | E7 |
imm8 | 2 | 2 | — |
COMR
Compare relative
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r0 | E8 |
rel8 | 2 | 3 | — |
| r1 | E9 |
rel8 | 2 | 3 | — |
| r2 | EA |
rel8 | 2 | 3 | — |
| r3 | EB |
rel8 | 2 | 3 | — |
COMA
Compare absolute
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r0 | EC |
addr16 | 3 | 4 | — |
| r1 | ED |
addr16 | 3 | 4 | — |
| r2 | EE |
addr16 | 3 | 4 | — |
| r3 | EF |
addr16 | 3 | 4 | — |
RRR
Rotate register right
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r0 | 50 |
— | 1 | 2 | — |
| r1 | 51 |
— | 1 | 2 | — |
| r2 | 52 |
— | 1 | 2 | — |
| r3 | 53 |
— | 1 | 2 | — |
RRL
Rotate register left
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r0 | D0 |
— | 1 | 2 | — |
| r1 | D1 |
— | 1 | 2 | — |
| r2 | D2 |
— | 1 | 2 | — |
| r3 | D3 |
— | 1 | 2 | — |
BCTR
Branch on condition true, relative
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| eq | 18 |
rel8 | 2 | 3 | — |
| gt | 19 |
rel8 | 2 | 3 | — |
| lt | 1A |
rel8 | 2 | 3 | — |
| un | 1B |
rel8 | 2 | 3 | — |
BCTA
Branch on condition true, absolute
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| eq | 1C |
addr16 | 3 | 3 | — |
| gt | 1D |
addr16 | 3 | 3 | — |
| lt | 1E |
addr16 | 3 | 3 | — |
| un | 1F |
addr16 | 3 | 3 | — |
BCFR
Branch on condition false, relative
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| eq | 98 |
rel8 | 2 | 3 | — |
| gt | 99 |
rel8 | 2 | 3 | — |
| lt | 9A |
rel8 | 2 | 3 | — |
| un | 9B |
rel8 | 2 | 3 | — |
BCFA
Branch on condition false, absolute
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| eq | 9C |
addr16 | 3 | 3 | — |
| gt | 9D |
addr16 | 3 | 3 | — |
| lt | 9E |
addr16 | 3 | 3 | — |
| un | 9F |
addr16 | 3 | 3 | — |
BSTR
Branch to subroutine on condition true, relative
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| eq | 38 |
rel8 | 2 | 3 | — |
| gt | 39 |
rel8 | 2 | 3 | — |
| lt | 3A |
rel8 | 2 | 3 | — |
| un | 3B |
rel8 | 2 | 3 | — |
BSTA
Branch to subroutine on condition true, absolute
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| eq | 3C |
addr16 | 3 | 3 | — |
| gt | 3D |
addr16 | 3 | 3 | — |
| lt | 3E |
addr16 | 3 | 3 | — |
| un | 3F |
addr16 | 3 | 3 | — |
BSFR
Branch to subroutine on condition false, relative
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| eq | B8 |
rel8 | 2 | 3 | — |
| gt | B9 |
rel8 | 2 | 3 | — |
| lt | BA |
rel8 | 2 | 3 | — |
| un | BB |
rel8 | 2 | 3 | — |
BSFA
Branch to subroutine on condition false, absolute
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| eq | BC |
addr16 | 3 | 3 | — |
| gt | BD |
addr16 | 3 | 3 | — |
| lt | BE |
addr16 | 3 | 3 | — |
| un | BF |
addr16 | 3 | 3 | — |
BRNR
Branch on register non-zero, relative
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r0 | 58 |
rel8 | 2 | 3 | — |
| r1 | 59 |
rel8 | 2 | 3 | — |
| r2 | 5A |
rel8 | 2 | 3 | — |
| r3 | 5B |
rel8 | 2 | 3 | — |
BRNA
Branch on register non-zero, absolute
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r0 | 5C |
addr16 | 3 | 3 | — |
| r1 | 5D |
addr16 | 3 | 3 | — |
| r2 | 5E |
addr16 | 3 | 3 | — |
| r3 | 5F |
addr16 | 3 | 3 | — |
BIRR
Branch on incrementing register, relative
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r0 | D8 |
rel8 | 2 | 3 | — |
| r1 | D9 |
rel8 | 2 | 3 | — |
| r2 | DA |
rel8 | 2 | 3 | — |
| r3 | DB |
rel8 | 2 | 3 | — |
BIRA
Branch on incrementing register, absolute
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r0 | DC |
addr16 | 3 | 3 | — |
| r1 | DD |
addr16 | 3 | 3 | — |
| r2 | DE |
addr16 | 3 | 3 | — |
| r3 | DF |
addr16 | 3 | 3 | — |
BDRR
Branch on decrementing register, relative
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r0 | F8 |
rel8 | 2 | 3 | — |
| r1 | F9 |
rel8 | 2 | 3 | — |
| r2 | FA |
rel8 | 2 | 3 | — |
| r3 | FB |
rel8 | 2 | 3 | — |
BDRA
Branch on decrementing register, absolute
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r0 | FC |
addr16 | 3 | 3 | — |
| r1 | FD |
addr16 | 3 | 3 | — |
| r2 | FE |
addr16 | 3 | 3 | — |
| r3 | FF |
addr16 | 3 | 3 | — |
BSNR
Branch to subroutine on non-zero register, relative
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r0 | 78 |
rel8 | 2 | 3 | — |
| r1 | 79 |
rel8 | 2 | 3 | — |
| r2 | 7A |
rel8 | 2 | 3 | — |
| r3 | 7B |
rel8 | 2 | 3 | — |
BSNA
Branch to subroutine on non-zero register, absolute
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r0 | 7C |
addr16 | 3 | 3 | — |
| r1 | 7D |
addr16 | 3 | 3 | — |
| r2 | 7E |
addr16 | 3 | 3 | — |
| r3 | 7F |
addr16 | 3 | 3 | — |
RETC
Return from subroutine, conditional
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| eq | 14 |
— | 1 | 3 | — |
| gt | 15 |
— | 1 | 3 | — |
| lt | 16 |
— | 1 | 3 | — |
| un | 17 |
— | 1 | 3 | — |
RETE
Return and enable interrupt, conditional
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| eq | 34 |
— | 1 | 3 | — |
| gt | 35 |
— | 1 | 3 | — |
| lt | 36 |
— | 1 | 3 | — |
| un | 37 |
— | 1 | 3 | — |
REDC
Read control
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r0 | 30 |
— | 1 | 2 | — |
| r1 | 31 |
— | 1 | 2 | — |
| r2 | 32 |
— | 1 | 2 | — |
| r3 | 33 |
— | 1 | 2 | — |
REDD
Read data
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r0 | 70 |
— | 1 | 2 | — |
| r1 | 71 |
— | 1 | 2 | — |
| r2 | 72 |
— | 1 | 2 | — |
| r3 | 73 |
— | 1 | 2 | — |
WRTC
Write control
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r0 | B0 |
— | 1 | 2 | — |
| r1 | B1 |
— | 1 | 2 | — |
| r2 | B2 |
— | 1 | 2 | — |
| r3 | B3 |
— | 1 | 2 | — |
WRTD
Write data
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r0 | F0 |
— | 1 | 2 | — |
| r1 | F1 |
— | 1 | 2 | — |
| r2 | F2 |
— | 1 | 2 | — |
| r3 | F3 |
— | 1 | 2 | — |
REDE
Read extended
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r0 | 54 |
imm8 | 2 | 3 | — |
| r1 | 55 |
imm8 | 2 | 3 | — |
| r2 | 56 |
imm8 | 2 | 3 | — |
| r3 | 57 |
imm8 | 2 | 3 | — |
WRTE
Write extended
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r0 | D4 |
imm8 | 2 | 3 | — |
| r1 | D5 |
imm8 | 2 | 3 | — |
| r2 | D6 |
imm8 | 2 | 3 | — |
| r3 | D7 |
imm8 | 2 | 3 | — |
LPSU
Load program status, upper
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
92 |
— | 1 | 2 | — |
LPSL
Load program status, lower
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
93 |
— | 1 | 2 | — |
SPSU
Store program status, upper
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
12 |
— | 1 | 2 | — |
SPSL
Store program status, lower
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
13 |
— | 1 | 2 | — |
CPSU
Clear program status, upper, masked
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
74 |
imm8 | 2 | 3 | — |
CPSL
Clear program status, lower, masked
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
75 |
imm8 | 2 | 3 | — |
PPSU
Preset program status, upper, masked
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
76 |
imm8 | 2 | 3 | — |
PPSL
Preset program status, lower, masked
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
77 |
imm8 | 2 | 3 | — |
TPSU
Test program status, upper, masked
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
B4 |
imm8 | 2 | 3 | — |
TPSL
Test program status, lower, masked
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
B5 |
imm8 | 2 | 3 | — |
HALT
Halt, enter wait state
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
40 |
— | 1 | 2 | — |
NOP
No operation
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
C0 |
— | 1 | 2 | — |
TMI
Test under mask immediate
| Mode | Opcode | Operands | Bytes | Cycles | Flags |
|---|---|---|---|---|---|
| r0 | F4 |
imm8 | 2 | 3 | — |
| r1 | F5 |
imm8 | 2 | 3 | — |
| r2 | F6 |
imm8 | 2 | 3 | — |
| r3 | F7 |
imm8 | 2 | 3 | — |
Machines
Interton VC 4000, Emerson Arcadia 2001
Sources
Encodings on this page were taken from:
- Signetics 2650 Microprocessor Manual — Signetics