Reference

Zilog Z80

140 mnemonics, 796 encoded forms, operands little-endian. Generated from crates/isa/src/z80.rs.

100 of those forms are undocumented opcodes, marked undocumented below. They encode, because real programs use them.

Cycle counts show the base cost; +p is an extra cycle when an indexed access crosses a page boundary, +t when a branch is taken.

NOP

No operation

Mode Opcode Operands Bytes Cycles Flags
00 1 4

LD

Load

Mode Opcode Operands Bytes Cycles Flags
B,B 40 1 4
B,C 41 1 4
B,D 42 1 4
B,E 43 1 4
B,H 44 1 4
B,L 45 1 4
B,(HL) 46 1 7
B,A 47 1 4
C,B 48 1 4
C,C 49 1 4
C,D 4A 1 4
C,E 4B 1 4
C,H 4C 1 4
C,L 4D 1 4
C,(HL) 4E 1 7
C,A 4F 1 4
D,B 50 1 4
D,C 51 1 4
D,D 52 1 4
D,E 53 1 4
D,H 54 1 4
D,L 55 1 4
D,(HL) 56 1 7
D,A 57 1 4
E,B 58 1 4
E,C 59 1 4
E,D 5A 1 4
E,E 5B 1 4
E,H 5C 1 4
E,L 5D 1 4
E,(HL) 5E 1 7
E,A 5F 1 4
H,B 60 1 4
H,C 61 1 4
H,D 62 1 4
H,E 63 1 4
H,H 64 1 4
H,L 65 1 4
H,(HL) 66 1 7
H,A 67 1 4
L,B 68 1 4
L,C 69 1 4
L,D 6A 1 4
L,E 6B 1 4
L,H 6C 1 4
L,L 6D 1 4
L,(HL) 6E 1 7
L,A 6F 1 4
(HL),B 70 1 7
(HL),C 71 1 7
(HL),D 72 1 7
(HL),E 73 1 7
(HL),H 74 1 7
(HL),L 75 1 7
(HL),A 77 1 7
A,B 78 1 4
A,C 79 1 4
A,D 7A 1 4
A,E 7B 1 4
A,H 7C 1 4
A,L 7D 1 4
A,(HL) 7E 1 7
A,A 7F 1 4
B,n 06 imm8 2 7
C,n 0E imm8 2 7
D,n 16 imm8 2 7
E,n 1E imm8 2 7
H,n 26 imm8 2 7
L,n 2E imm8 2 7
(HL),n 36 imm8 2 10
A,n 3E imm8 2 7
BC,nn 01 imm16 3 10
DE,nn 11 imm16 3 10
HL,nn 21 imm16 3 10
SP,nn 31 imm16 3 10
(BC),A 02 1 7
(DE),A 12 1 7
A,(BC) 0A 1 7
A,(DE) 1A 1 7
(nn),HL 22 addr16 3 16
HL,(nn) 2A addr16 3 16
(nn),A 32 addr16 3 13
A,(nn) 3A addr16 3 13
SP,HL F9 1 6
(nn),BC ED 43 addr16 4 20
BC,(nn) ED 4B addr16 4 20
(nn),DE ED 53 addr16 4 20
DE,(nn) ED 5B addr16 4 20
(nn),SP ED 73 addr16 4 20
SP,(nn) ED 7B addr16 4 20
I,A ED 47 2 9
R,A ED 4F 2 9
A,I ED 57 2 9 SZHPN
A,R ED 5F 2 9 SZHPN

EX

Exchange

Mode Opcode Operands Bytes Cycles Flags
AF,AF’ 08 1 4
DE,HL EB 1 4
(SP),HL E3 1 19

DJNZ

Decrement B and jump if not zero

Mode Opcode Operands Bytes Cycles Flags
e 10 rel8 2 8 +t

JR

Jump relative

Mode Opcode Operands Bytes Cycles Flags
e 18 rel8 2 7 +t
NZ,e 20 rel8 2 7 +t
Z,e 28 rel8 2 7 +t
NC,e 30 rel8 2 7 +t
C,e 38 rel8 2 7 +t

ADD

Add

Mode Opcode Operands Bytes Cycles Flags
HL,BC 09 1 11 HNC
HL,DE 19 1 11 HNC
HL,HL 29 1 11 HNC
HL,SP 39 1 11 HNC
A,B 80 1 4 SZHPNC
A,C 81 1 4 SZHPNC
A,D 82 1 4 SZHPNC
A,E 83 1 4 SZHPNC
A,H 84 1 4 SZHPNC
A,L 85 1 4 SZHPNC
A,(HL) 86 1 7 SZHPNC
A,A 87 1 4 SZHPNC
A,n C6 imm8 2 7 SZHPNC

ADC

Add with carry

Mode Opcode Operands Bytes Cycles Flags
A,B 88 1 4 SZHPNC
A,C 89 1 4 SZHPNC
A,D 8A 1 4 SZHPNC
A,E 8B 1 4 SZHPNC
A,H 8C 1 4 SZHPNC
A,L 8D 1 4 SZHPNC
A,(HL) 8E 1 7 SZHPNC
A,A 8F 1 4 SZHPNC
A,n CE imm8 2 7 SZHPNC
HL,BC ED 4A 2 15 SZHPNC
HL,DE ED 5A 2 15 SZHPNC
HL,HL ED 6A 2 15 SZHPNC
HL,SP ED 7A 2 15 SZHPNC

SUB

Subtract

Mode Opcode Operands Bytes Cycles Flags
B 90 1 4 SZHPNC
C 91 1 4 SZHPNC
D 92 1 4 SZHPNC
E 93 1 4 SZHPNC
H 94 1 4 SZHPNC
L 95 1 4 SZHPNC
(HL) 96 1 7 SZHPNC
A 97 1 4 SZHPNC
n D6 imm8 2 7 SZHPNC

SBC

Subtract with carry

Mode Opcode Operands Bytes Cycles Flags
A,B 98 1 4 SZHPNC
A,C 99 1 4 SZHPNC
A,D 9A 1 4 SZHPNC
A,E 9B 1 4 SZHPNC
A,H 9C 1 4 SZHPNC
A,L 9D 1 4 SZHPNC
A,(HL) 9E 1 7 SZHPNC
A,A 9F 1 4 SZHPNC
A,n DE imm8 2 7 SZHPNC
HL,BC ED 42 2 15 SZHPNC
HL,DE ED 52 2 15 SZHPNC
HL,HL ED 62 2 15 SZHPNC
HL,SP ED 72 2 15 SZHPNC

AND

Logical AND

Mode Opcode Operands Bytes Cycles Flags
B A0 1 4 SZHPNC
C A1 1 4 SZHPNC
D A2 1 4 SZHPNC
E A3 1 4 SZHPNC
H A4 1 4 SZHPNC
L A5 1 4 SZHPNC
(HL) A6 1 7 SZHPNC
A A7 1 4 SZHPNC
n E6 imm8 2 7 SZHPNC

XOR

Logical exclusive OR

Mode Opcode Operands Bytes Cycles Flags
B A8 1 4 SZHPNC
C A9 1 4 SZHPNC
D AA 1 4 SZHPNC
E AB 1 4 SZHPNC
H AC 1 4 SZHPNC
L AD 1 4 SZHPNC
(HL) AE 1 7 SZHPNC
A AF 1 4 SZHPNC
n EE imm8 2 7 SZHPNC

OR

Logical inclusive OR

Mode Opcode Operands Bytes Cycles Flags
B B0 1 4 SZHPNC
C B1 1 4 SZHPNC
D B2 1 4 SZHPNC
E B3 1 4 SZHPNC
H B4 1 4 SZHPNC
L B5 1 4 SZHPNC
(HL) B6 1 7 SZHPNC
A B7 1 4 SZHPNC
n F6 imm8 2 7 SZHPNC

CP

Compare with A

Mode Opcode Operands Bytes Cycles Flags
B B8 1 4 SZHPNC
C B9 1 4 SZHPNC
D BA 1 4 SZHPNC
E BB 1 4 SZHPNC
H BC 1 4 SZHPNC
L BD 1 4 SZHPNC
(HL) BE 1 7 SZHPNC
A BF 1 4 SZHPNC
n FE imm8 2 7 SZHPNC

INC

Increment

Mode Opcode Operands Bytes Cycles Flags
BC 03 1 6
DE 13 1 6
HL 23 1 6
SP 33 1 6
B 04 1 4 SZHPN
C 0C 1 4 SZHPN
D 14 1 4 SZHPN
E 1C 1 4 SZHPN
H 24 1 4 SZHPN
L 2C 1 4 SZHPN
(HL) 34 1 11 SZHPN
A 3C 1 4 SZHPN

DEC

Decrement

Mode Opcode Operands Bytes Cycles Flags
BC 0B 1 6
DE 1B 1 6
HL 2B 1 6
SP 3B 1 6
B 05 1 4 SZHPN
C 0D 1 4 SZHPN
D 15 1 4 SZHPN
E 1D 1 4 SZHPN
H 25 1 4 SZHPN
L 2D 1 4 SZHPN
(HL) 35 1 11 SZHPN
A 3D 1 4 SZHPN

RLCA

Rotate A left circular

Mode Opcode Operands Bytes Cycles Flags
07 1 4 HNC

RRCA

Rotate A right circular

Mode Opcode Operands Bytes Cycles Flags
0F 1 4 HNC

RLA

Rotate A left through carry

Mode Opcode Operands Bytes Cycles Flags
17 1 4 HNC

RRA

Rotate A right through carry

Mode Opcode Operands Bytes Cycles Flags
1F 1 4 HNC

DAA

Decimal adjust A

Mode Opcode Operands Bytes Cycles Flags
27 1 4 SZHPC

CPL

Complement A

Mode Opcode Operands Bytes Cycles Flags
2F 1 4 HN

SCF

Set carry flag

Mode Opcode Operands Bytes Cycles Flags
37 1 4 HNC

CCF

Complement carry flag

Mode Opcode Operands Bytes Cycles Flags
3F 1 4 HNC

HALT

Halt

Mode Opcode Operands Bytes Cycles Flags
76 1 4

PUSH

Push register pair

Mode Opcode Operands Bytes Cycles Flags
BC C5 1 11
DE D5 1 11
HL E5 1 11
AF F5 1 11

POP

Pop register pair

Mode Opcode Operands Bytes Cycles Flags
BC C1 1 10
DE D1 1 10
HL E1 1 10
AF F1 1 10 SZHPNC

JP

Jump

Mode Opcode Operands Bytes Cycles Flags
nn C3 addr16 3 10
(HL) E9 1 4
NZ,nn C2 addr16 3 10
Z,nn CA addr16 3 10
NC,nn D2 addr16 3 10
C,nn DA addr16 3 10
PO,nn E2 addr16 3 10
PE,nn EA addr16 3 10
P,nn F2 addr16 3 10
M,nn FA addr16 3 10

CALL

Call subroutine

Mode Opcode Operands Bytes Cycles Flags
nn CD addr16 3 17
NZ,nn C4 addr16 3 10 +t
Z,nn CC addr16 3 10 +t
NC,nn D4 addr16 3 10 +t
C,nn DC addr16 3 10 +t
PO,nn E4 addr16 3 10 +t
PE,nn EC addr16 3 10 +t
P,nn F4 addr16 3 10 +t
M,nn FC addr16 3 10 +t

RET

Return

Mode Opcode Operands Bytes Cycles Flags
C9 1 10
NZ C0 1 5 +t
Z C8 1 5 +t
NC D0 1 5 +t
C D8 1 5 +t
PO E0 1 5 +t
PE E8 1 5 +t
P F0 1 5 +t
M F8 1 5 +t

RST

Restart

Mode Opcode Operands Bytes Cycles Flags
00 C7 1 11
08 CF 1 11
10 D7 1 11
18 DF 1 11
20 E7 1 11
28 EF 1 11
30 F7 1 11
38 FF 1 11

OUT

Output to port

Mode Opcode Operands Bytes Cycles Flags
(n),A D3 imm8 2 11
(C),B ED 41 2 12
(C),C ED 49 2 12
(C),D ED 51 2 12
(C),E ED 59 2 12
(C),H ED 61 2 12
(C),L ED 69 2 12
(C),A ED 79 2 12

IN

Input from port

Mode Opcode Operands Bytes Cycles Flags
A,(n) DB imm8 2 11
B,(C) ED 40 2 12 SZHPN
C,(C) ED 48 2 12 SZHPN
D,(C) ED 50 2 12 SZHPN
E,(C) ED 58 2 12 SZHPN
H,(C) ED 60 2 12 SZHPN
L,(C) ED 68 2 12 SZHPN
A,(C) ED 78 2 12 SZHPN

EXX

Exchange register set

Mode Opcode Operands Bytes Cycles Flags
D9 1 4

DI

Disable interrupts

Mode Opcode Operands Bytes Cycles Flags
F3 1 4

EI

Enable interrupts

Mode Opcode Operands Bytes Cycles Flags
FB 1 4

NEG

Negate accumulator

Mode Opcode Operands Bytes Cycles Flags
ED 44 2 8 SZHPNC

RETN

Return from NMI

Mode Opcode Operands Bytes Cycles Flags
ED 45 2 14

RETI

Return from interrupt

Mode Opcode Operands Bytes Cycles Flags
ED 4D 2 14

RRD

Rotate right decimal

Mode Opcode Operands Bytes Cycles Flags
ED 67 2 18 SZHPN

RLD

Rotate left decimal

Mode Opcode Operands Bytes Cycles Flags
ED 6F 2 18 SZHPN

IM

Set interrupt mode

Mode Opcode Operands Bytes Cycles Flags
0 ED 46 2 8
1 ED 56 2 8
2 ED 5E 2 8

LDI

Block load, increment

Mode Opcode Operands Bytes Cycles Flags
ED A0 2 16 HPN

LDD

Block load, decrement

Mode Opcode Operands Bytes Cycles Flags
ED A8 2 16 HPN

LDIR

Block load, inc, repeat

Mode Opcode Operands Bytes Cycles Flags
ED B0 2 16 +t HPN

LDDR

Block load, dec, repeat

Mode Opcode Operands Bytes Cycles Flags
ED B8 2 16 +t HPN

CPI

Block compare, increment

Mode Opcode Operands Bytes Cycles Flags
ED A1 2 16 SZHPN

CPD

Block compare, decrement

Mode Opcode Operands Bytes Cycles Flags
ED A9 2 16 SZHPN

CPIR

Block compare, inc, repeat

Mode Opcode Operands Bytes Cycles Flags
ED B1 2 16 +t SZHPN

CPDR

Block compare, dec, repeat

Mode Opcode Operands Bytes Cycles Flags
ED B9 2 16 +t SZHPN

INI

Block input, increment

Mode Opcode Operands Bytes Cycles Flags
ED A2 2 16 SZHPNC

IND

Block input, decrement

Mode Opcode Operands Bytes Cycles Flags
ED AA 2 16 SZHPNC

INIR

Block input, inc, repeat

Mode Opcode Operands Bytes Cycles Flags
ED B2 2 16 +t SZHPNC

INDR

Block input, dec, repeat

Mode Opcode Operands Bytes Cycles Flags
ED BA 2 16 +t SZHPNC

OUTI

Block output, increment

Mode Opcode Operands Bytes Cycles Flags
ED A3 2 16 SZHPNC

OUTD

Block output, decrement

Mode Opcode Operands Bytes Cycles Flags
ED AB 2 16 SZHPNC

OTIR

Block output, inc, repeat

Mode Opcode Operands Bytes Cycles Flags
ED B3 2 16 +t SZHPNC

OTDR

Block output, dec, repeat

Mode Opcode Operands Bytes Cycles Flags
ED BB 2 16 +t SZHPNC

RLC

Rotate left circular

Mode Opcode Operands Bytes Cycles Flags
B CB 00 2 8 SZHPNC
C CB 01 2 8 SZHPNC
D CB 02 2 8 SZHPNC
E CB 03 2 8 SZHPNC
H CB 04 2 8 SZHPNC
L CB 05 2 8 SZHPNC
(HL) CB 06 2 15 SZHPNC
A CB 07 2 8 SZHPNC

RRC

Rotate right circular

Mode Opcode Operands Bytes Cycles Flags
B CB 08 2 8 SZHPNC
C CB 09 2 8 SZHPNC
D CB 0A 2 8 SZHPNC
E CB 0B 2 8 SZHPNC
H CB 0C 2 8 SZHPNC
L CB 0D 2 8 SZHPNC
(HL) CB 0E 2 15 SZHPNC
A CB 0F 2 8 SZHPNC

RL

Rotate left through carry

Mode Opcode Operands Bytes Cycles Flags
B CB 10 2 8 SZHPNC
C CB 11 2 8 SZHPNC
D CB 12 2 8 SZHPNC
E CB 13 2 8 SZHPNC
H CB 14 2 8 SZHPNC
L CB 15 2 8 SZHPNC
(HL) CB 16 2 15 SZHPNC
A CB 17 2 8 SZHPNC

RR

Rotate right through carry

Mode Opcode Operands Bytes Cycles Flags
B CB 18 2 8 SZHPNC
C CB 19 2 8 SZHPNC
D CB 1A 2 8 SZHPNC
E CB 1B 2 8 SZHPNC
H CB 1C 2 8 SZHPNC
L CB 1D 2 8 SZHPNC
(HL) CB 1E 2 15 SZHPNC
A CB 1F 2 8 SZHPNC

SLA

Shift left arithmetic

Mode Opcode Operands Bytes Cycles Flags
B CB 20 2 8 SZHPNC
C CB 21 2 8 SZHPNC
D CB 22 2 8 SZHPNC
E CB 23 2 8 SZHPNC
H CB 24 2 8 SZHPNC
L CB 25 2 8 SZHPNC
(HL) CB 26 2 15 SZHPNC
A CB 27 2 8 SZHPNC

SRA

Shift right arithmetic

Mode Opcode Operands Bytes Cycles Flags
B CB 28 2 8 SZHPNC
C CB 29 2 8 SZHPNC
D CB 2A 2 8 SZHPNC
E CB 2B 2 8 SZHPNC
H CB 2C 2 8 SZHPNC
L CB 2D 2 8 SZHPNC
(HL) CB 2E 2 15 SZHPNC
A CB 2F 2 8 SZHPNC

SLL

Shift left logical (undocumented)

Mode Opcode Operands Bytes Cycles Flags
B undocumented CB 30 2 8 SZHPNC
C undocumented CB 31 2 8 SZHPNC
D undocumented CB 32 2 8 SZHPNC
E undocumented CB 33 2 8 SZHPNC
H undocumented CB 34 2 8 SZHPNC
L undocumented CB 35 2 8 SZHPNC
(HL) undocumented CB 36 2 15 SZHPNC
A undocumented CB 37 2 8 SZHPNC

SRL

Shift right logical

Mode Opcode Operands Bytes Cycles Flags
B CB 38 2 8 SZHPNC
C CB 39 2 8 SZHPNC
D CB 3A 2 8 SZHPNC
E CB 3B 2 8 SZHPNC
H CB 3C 2 8 SZHPNC
L CB 3D 2 8 SZHPNC
(HL) CB 3E 2 15 SZHPNC
A CB 3F 2 8 SZHPNC

BIT

Test bit

Mode Opcode Operands Bytes Cycles Flags
0,B CB 40 2 8 SZHPN
0,C CB 41 2 8 SZHPN
0,D CB 42 2 8 SZHPN
0,E CB 43 2 8 SZHPN
0,H CB 44 2 8 SZHPN
0,L CB 45 2 8 SZHPN
0,(HL) CB 46 2 12 SZHPN
0,A CB 47 2 8 SZHPN
1,B CB 48 2 8 SZHPN
1,C CB 49 2 8 SZHPN
1,D CB 4A 2 8 SZHPN
1,E CB 4B 2 8 SZHPN
1,H CB 4C 2 8 SZHPN
1,L CB 4D 2 8 SZHPN
1,(HL) CB 4E 2 12 SZHPN
1,A CB 4F 2 8 SZHPN
2,B CB 50 2 8 SZHPN
2,C CB 51 2 8 SZHPN
2,D CB 52 2 8 SZHPN
2,E CB 53 2 8 SZHPN
2,H CB 54 2 8 SZHPN
2,L CB 55 2 8 SZHPN
2,(HL) CB 56 2 12 SZHPN
2,A CB 57 2 8 SZHPN
3,B CB 58 2 8 SZHPN
3,C CB 59 2 8 SZHPN
3,D CB 5A 2 8 SZHPN
3,E CB 5B 2 8 SZHPN
3,H CB 5C 2 8 SZHPN
3,L CB 5D 2 8 SZHPN
3,(HL) CB 5E 2 12 SZHPN
3,A CB 5F 2 8 SZHPN
4,B CB 60 2 8 SZHPN
4,C CB 61 2 8 SZHPN
4,D CB 62 2 8 SZHPN
4,E CB 63 2 8 SZHPN
4,H CB 64 2 8 SZHPN
4,L CB 65 2 8 SZHPN
4,(HL) CB 66 2 12 SZHPN
4,A CB 67 2 8 SZHPN
5,B CB 68 2 8 SZHPN
5,C CB 69 2 8 SZHPN
5,D CB 6A 2 8 SZHPN
5,E CB 6B 2 8 SZHPN
5,H CB 6C 2 8 SZHPN
5,L CB 6D 2 8 SZHPN
5,(HL) CB 6E 2 12 SZHPN
5,A CB 6F 2 8 SZHPN
6,B CB 70 2 8 SZHPN
6,C CB 71 2 8 SZHPN
6,D CB 72 2 8 SZHPN
6,E CB 73 2 8 SZHPN
6,H CB 74 2 8 SZHPN
6,L CB 75 2 8 SZHPN
6,(HL) CB 76 2 12 SZHPN
6,A CB 77 2 8 SZHPN
7,B CB 78 2 8 SZHPN
7,C CB 79 2 8 SZHPN
7,D CB 7A 2 8 SZHPN
7,E CB 7B 2 8 SZHPN
7,H CB 7C 2 8 SZHPN
7,L CB 7D 2 8 SZHPN
7,(HL) CB 7E 2 12 SZHPN
7,A CB 7F 2 8 SZHPN

RES

Reset bit

Mode Opcode Operands Bytes Cycles Flags
0,B CB 80 2 8
0,C CB 81 2 8
0,D CB 82 2 8
0,E CB 83 2 8
0,H CB 84 2 8
0,L CB 85 2 8
0,(HL) CB 86 2 15
0,A CB 87 2 8
1,B CB 88 2 8
1,C CB 89 2 8
1,D CB 8A 2 8
1,E CB 8B 2 8
1,H CB 8C 2 8
1,L CB 8D 2 8
1,(HL) CB 8E 2 15
1,A CB 8F 2 8
2,B CB 90 2 8
2,C CB 91 2 8
2,D CB 92 2 8
2,E CB 93 2 8
2,H CB 94 2 8
2,L CB 95 2 8
2,(HL) CB 96 2 15
2,A CB 97 2 8
3,B CB 98 2 8
3,C CB 99 2 8
3,D CB 9A 2 8
3,E CB 9B 2 8
3,H CB 9C 2 8
3,L CB 9D 2 8
3,(HL) CB 9E 2 15
3,A CB 9F 2 8
4,B CB A0 2 8
4,C CB A1 2 8
4,D CB A2 2 8
4,E CB A3 2 8
4,H CB A4 2 8
4,L CB A5 2 8
4,(HL) CB A6 2 15
4,A CB A7 2 8
5,B CB A8 2 8
5,C CB A9 2 8
5,D CB AA 2 8
5,E CB AB 2 8
5,H CB AC 2 8
5,L CB AD 2 8
5,(HL) CB AE 2 15
5,A CB AF 2 8
6,B CB B0 2 8
6,C CB B1 2 8
6,D CB B2 2 8
6,E CB B3 2 8
6,H CB B4 2 8
6,L CB B5 2 8
6,(HL) CB B6 2 15
6,A CB B7 2 8
7,B CB B8 2 8
7,C CB B9 2 8
7,D CB BA 2 8
7,E CB BB 2 8
7,H CB BC 2 8
7,L CB BD 2 8
7,(HL) CB BE 2 15
7,A CB BF 2 8

SET

Set bit

Mode Opcode Operands Bytes Cycles Flags
0,B CB C0 2 8
0,C CB C1 2 8
0,D CB C2 2 8
0,E CB C3 2 8
0,H CB C4 2 8
0,L CB C5 2 8
0,(HL) CB C6 2 15
0,A CB C7 2 8
1,B CB C8 2 8
1,C CB C9 2 8
1,D CB CA 2 8
1,E CB CB 2 8
1,H CB CC 2 8
1,L CB CD 2 8
1,(HL) CB CE 2 15
1,A CB CF 2 8
2,B CB D0 2 8
2,C CB D1 2 8
2,D CB D2 2 8
2,E CB D3 2 8
2,H CB D4 2 8
2,L CB D5 2 8
2,(HL) CB D6 2 15
2,A CB D7 2 8
3,B CB D8 2 8
3,C CB D9 2 8
3,D CB DA 2 8
3,E CB DB 2 8
3,H CB DC 2 8
3,L CB DD 2 8
3,(HL) CB DE 2 15
3,A CB DF 2 8
4,B CB E0 2 8
4,C CB E1 2 8
4,D CB E2 2 8
4,E CB E3 2 8
4,H CB E4 2 8
4,L CB E5 2 8
4,(HL) CB E6 2 15
4,A CB E7 2 8
5,B CB E8 2 8
5,C CB E9 2 8
5,D CB EA 2 8
5,E CB EB 2 8
5,H CB EC 2 8
5,L CB ED 2 8
5,(HL) CB EE 2 15
5,A CB EF 2 8
6,B CB F0 2 8
6,C CB F1 2 8
6,D CB F2 2 8
6,E CB F3 2 8
6,H CB F4 2 8
6,L CB F5 2 8
6,(HL) CB F6 2 15
6,A CB F7 2 8
7,B CB F8 2 8
7,C CB F9 2 8
7,D CB FA 2 8
7,E CB FB 2 8
7,H CB FC 2 8
7,L CB FD 2 8
7,(HL) CB FE 2 15
7,A CB FF 2 8

LD

Load IX byte halves

Mode Opcode Operands Bytes Cycles Flags
B,IXH undocumented DD 44 2 8
B,IXL undocumented DD 45 2 8
C,IXH undocumented DD 4C 2 8
C,IXL undocumented DD 4D 2 8
D,IXH undocumented DD 54 2 8
D,IXL undocumented DD 55 2 8
E,IXH undocumented DD 5C 2 8
E,IXL undocumented DD 5D 2 8
IXH,B undocumented DD 60 2 8
IXH,C undocumented DD 61 2 8
IXH,D undocumented DD 62 2 8
IXH,E undocumented DD 63 2 8
IXH,IXH undocumented DD 64 2 8
IXH,IXL undocumented DD 65 2 8
IXH,A undocumented DD 67 2 8
IXL,B undocumented DD 68 2 8
IXL,C undocumented DD 69 2 8
IXL,D undocumented DD 6A 2 8
IXL,E undocumented DD 6B 2 8
IXL,IXH undocumented DD 6C 2 8
IXL,IXL undocumented DD 6D 2 8
IXL,A undocumented DD 6F 2 8
A,IXH undocumented DD 7C 2 8
A,IXL undocumented DD 7D 2 8
IXH,n undocumented DD 26 imm8 3 11
IXL,n undocumented DD 2E imm8 3 11

INC

Increment IX byte halves

Mode Opcode Operands Bytes Cycles Flags
IXH undocumented DD 24 2 8 SZHPN
IXL undocumented DD 2C 2 8 SZHPN

DEC

Decrement IX byte halves

Mode Opcode Operands Bytes Cycles Flags
IXH undocumented DD 25 2 8 SZHPN
IXL undocumented DD 2D 2 8 SZHPN

ADD

ADD IX byte halves

Mode Opcode Operands Bytes Cycles Flags
A,IXH undocumented DD 84 2 8 SZHPNC
A,IXL undocumented DD 85 2 8 SZHPNC

ADC

ADC IX byte halves

Mode Opcode Operands Bytes Cycles Flags
A,IXH undocumented DD 8C 2 8 SZHPNC
A,IXL undocumented DD 8D 2 8 SZHPNC

SUB

SUB IX byte halves

Mode Opcode Operands Bytes Cycles Flags
IXH undocumented DD 94 2 8 SZHPNC
IXL undocumented DD 95 2 8 SZHPNC

SBC

SBC IX byte halves

Mode Opcode Operands Bytes Cycles Flags
A,IXH undocumented DD 9C 2 8 SZHPNC
A,IXL undocumented DD 9D 2 8 SZHPNC

AND

AND IX byte halves

Mode Opcode Operands Bytes Cycles Flags
IXH undocumented DD A4 2 8 SZHPNC
IXL undocumented DD A5 2 8 SZHPNC

XOR

XOR IX byte halves

Mode Opcode Operands Bytes Cycles Flags
IXH undocumented DD AC 2 8 SZHPNC
IXL undocumented DD AD 2 8 SZHPNC

OR

OR IX byte halves

Mode Opcode Operands Bytes Cycles Flags
IXH undocumented DD B4 2 8 SZHPNC
IXL undocumented DD B5 2 8 SZHPNC

CP

CP IX byte halves

Mode Opcode Operands Bytes Cycles Flags
IXH undocumented DD BC 2 8 SZHPNC
IXL undocumented DD BD 2 8 SZHPNC

LD

Load IY byte halves

Mode Opcode Operands Bytes Cycles Flags
B,IYH undocumented FD 44 2 8
B,IYL undocumented FD 45 2 8
C,IYH undocumented FD 4C 2 8
C,IYL undocumented FD 4D 2 8
D,IYH undocumented FD 54 2 8
D,IYL undocumented FD 55 2 8
E,IYH undocumented FD 5C 2 8
E,IYL undocumented FD 5D 2 8
IYH,B undocumented FD 60 2 8
IYH,C undocumented FD 61 2 8
IYH,D undocumented FD 62 2 8
IYH,E undocumented FD 63 2 8
IYH,IYH undocumented FD 64 2 8
IYH,IYL undocumented FD 65 2 8
IYH,A undocumented FD 67 2 8
IYL,B undocumented FD 68 2 8
IYL,C undocumented FD 69 2 8
IYL,D undocumented FD 6A 2 8
IYL,E undocumented FD 6B 2 8
IYL,IYH undocumented FD 6C 2 8
IYL,IYL undocumented FD 6D 2 8
IYL,A undocumented FD 6F 2 8
A,IYH undocumented FD 7C 2 8
A,IYL undocumented FD 7D 2 8
IYH,n undocumented FD 26 imm8 3 11
IYL,n undocumented FD 2E imm8 3 11

INC

Increment IY byte halves

Mode Opcode Operands Bytes Cycles Flags
IYH undocumented FD 24 2 8 SZHPN
IYL undocumented FD 2C 2 8 SZHPN

DEC

Decrement IY byte halves

Mode Opcode Operands Bytes Cycles Flags
IYH undocumented FD 25 2 8 SZHPN
IYL undocumented FD 2D 2 8 SZHPN

ADD

ADD IY byte halves

Mode Opcode Operands Bytes Cycles Flags
A,IYH undocumented FD 84 2 8 SZHPNC
A,IYL undocumented FD 85 2 8 SZHPNC

ADC

ADC IY byte halves

Mode Opcode Operands Bytes Cycles Flags
A,IYH undocumented FD 8C 2 8 SZHPNC
A,IYL undocumented FD 8D 2 8 SZHPNC

SUB

SUB IY byte halves

Mode Opcode Operands Bytes Cycles Flags
IYH undocumented FD 94 2 8 SZHPNC
IYL undocumented FD 95 2 8 SZHPNC

SBC

SBC IY byte halves

Mode Opcode Operands Bytes Cycles Flags
A,IYH undocumented FD 9C 2 8 SZHPNC
A,IYL undocumented FD 9D 2 8 SZHPNC

AND

AND IY byte halves

Mode Opcode Operands Bytes Cycles Flags
IYH undocumented FD A4 2 8 SZHPNC
IYL undocumented FD A5 2 8 SZHPNC

XOR

XOR IY byte halves

Mode Opcode Operands Bytes Cycles Flags
IYH undocumented FD AC 2 8 SZHPNC
IYL undocumented FD AD 2 8 SZHPNC

OR

OR IY byte halves

Mode Opcode Operands Bytes Cycles Flags
IYH undocumented FD B4 2 8 SZHPNC
IYL undocumented FD B5 2 8 SZHPNC

CP

CP IY byte halves

Mode Opcode Operands Bytes Cycles Flags
IYH undocumented FD BC 2 8 SZHPNC
IYL undocumented FD BD 2 8 SZHPNC

ADD

Add to IX

Mode Opcode Operands Bytes Cycles Flags
IX,BC DD 09 2 15 HNC
IX,DE DD 19 2 15 HNC
IX,IX DD 29 2 15 HNC
IX,SP DD 39 2 15 HNC
A,(IX+d) DD 86 disp8 3 19 SZHPNC

ADC

Add with carry, IX

Mode Opcode Operands Bytes Cycles Flags
A,(IX+d) DD 8E disp8 3 19 SZHPNC

SUB

Subtract, IX

Mode Opcode Operands Bytes Cycles Flags
(IX+d) DD 96 disp8 3 19 SZHPNC

SBC

Subtract carry, IX

Mode Opcode Operands Bytes Cycles Flags
A,(IX+d) DD 9E disp8 3 19 SZHPNC

AND

AND, IX

Mode Opcode Operands Bytes Cycles Flags
(IX+d) DD A6 disp8 3 19 SZHPNC

XOR

XOR, IX

Mode Opcode Operands Bytes Cycles Flags
(IX+d) DD AE disp8 3 19 SZHPNC

OR

OR, IX

Mode Opcode Operands Bytes Cycles Flags
(IX+d) DD B6 disp8 3 19 SZHPNC

CP

Compare, IX

Mode Opcode Operands Bytes Cycles Flags
(IX+d) DD BE disp8 3 19 SZHPNC

INC

Increment IX

Mode Opcode Operands Bytes Cycles Flags
IX DD 23 2 10
(IX+d) DD 34 disp8 3 23 SZHPN

DEC

Decrement IX

Mode Opcode Operands Bytes Cycles Flags
IX DD 2B 2 10
(IX+d) DD 35 disp8 3 23 SZHPN

PUSH

Push IX

Mode Opcode Operands Bytes Cycles Flags
IX DD E5 2 15

POP

Pop IX

Mode Opcode Operands Bytes Cycles Flags
IX DD E1 2 14

EX

Exchange IX

Mode Opcode Operands Bytes Cycles Flags
(SP),IX DD E3 2 23

JP

Jump IX

Mode Opcode Operands Bytes Cycles Flags
(IX) DD E9 2 8

LD

Load IX

Mode Opcode Operands Bytes Cycles Flags
IX,nn DD 21 imm16 4 14
(nn),IX DD 22 addr16 4 20
IX,(nn) DD 2A addr16 4 20
SP,IX DD F9 2 10
(IX+d),n DD 36 disp8, imm8 4 19
B,(IX+d) DD 46 disp8 3 19
C,(IX+d) DD 4E disp8 3 19
D,(IX+d) DD 56 disp8 3 19
E,(IX+d) DD 5E disp8 3 19
H,(IX+d) DD 66 disp8 3 19
L,(IX+d) DD 6E disp8 3 19
A,(IX+d) DD 7E disp8 3 19
(IX+d),B DD 70 disp8 3 19
(IX+d),C DD 71 disp8 3 19
(IX+d),D DD 72 disp8 3 19
(IX+d),E DD 73 disp8 3 19
(IX+d),H DD 74 disp8 3 19
(IX+d),L DD 75 disp8 3 19
(IX+d),A DD 77 disp8 3 19

RLC

Rotate left circular (IX+d)

Mode Opcode Operands Bytes Cycles Flags
(IX+d) DD CB .. 06 disp8 4 23 SZHPNC

RRC

Rotate right circular (IX+d)

Mode Opcode Operands Bytes Cycles Flags
(IX+d) DD CB .. 0E disp8 4 23 SZHPNC

RL

Rotate left (IX+d)

Mode Opcode Operands Bytes Cycles Flags
(IX+d) DD CB .. 16 disp8 4 23 SZHPNC

RR

Rotate right (IX+d)

Mode Opcode Operands Bytes Cycles Flags
(IX+d) DD CB .. 1E disp8 4 23 SZHPNC

SLA

Shift left arithmetic (IX+d)

Mode Opcode Operands Bytes Cycles Flags
(IX+d) DD CB .. 26 disp8 4 23 SZHPNC

SRA

Shift right arithmetic (IX+d)

Mode Opcode Operands Bytes Cycles Flags
(IX+d) DD CB .. 2E disp8 4 23 SZHPNC

SRL

Shift right logical (IX+d)

Mode Opcode Operands Bytes Cycles Flags
(IX+d) DD CB .. 3E disp8 4 23 SZHPNC

BIT

Test bit (IX+d)

Mode Opcode Operands Bytes Cycles Flags
0,(IX+d) DD CB .. 46 disp8 4 20 SZHPN
1,(IX+d) DD CB .. 4E disp8 4 20 SZHPN
2,(IX+d) DD CB .. 56 disp8 4 20 SZHPN
3,(IX+d) DD CB .. 5E disp8 4 20 SZHPN
4,(IX+d) DD CB .. 66 disp8 4 20 SZHPN
5,(IX+d) DD CB .. 6E disp8 4 20 SZHPN
6,(IX+d) DD CB .. 76 disp8 4 20 SZHPN
7,(IX+d) DD CB .. 7E disp8 4 20 SZHPN

RES

Reset bit (IX+d)

Mode Opcode Operands Bytes Cycles Flags
0,(IX+d) DD CB .. 86 disp8 4 23
1,(IX+d) DD CB .. 8E disp8 4 23
2,(IX+d) DD CB .. 96 disp8 4 23
3,(IX+d) DD CB .. 9E disp8 4 23
4,(IX+d) DD CB .. A6 disp8 4 23
5,(IX+d) DD CB .. AE disp8 4 23
6,(IX+d) DD CB .. B6 disp8 4 23
7,(IX+d) DD CB .. BE disp8 4 23

SET

Set bit (IX+d)

Mode Opcode Operands Bytes Cycles Flags
0,(IX+d) DD CB .. C6 disp8 4 23
1,(IX+d) DD CB .. CE disp8 4 23
2,(IX+d) DD CB .. D6 disp8 4 23
3,(IX+d) DD CB .. DE disp8 4 23
4,(IX+d) DD CB .. E6 disp8 4 23
5,(IX+d) DD CB .. EE disp8 4 23
6,(IX+d) DD CB .. F6 disp8 4 23
7,(IX+d) DD CB .. FE disp8 4 23

ADD

Add to IY

Mode Opcode Operands Bytes Cycles Flags
IY,BC FD 09 2 15 HNC
IY,DE FD 19 2 15 HNC
IY,IY FD 29 2 15 HNC
IY,SP FD 39 2 15 HNC
A,(IY+d) FD 86 disp8 3 19 SZHPNC

ADC

Add with carry, IY

Mode Opcode Operands Bytes Cycles Flags
A,(IY+d) FD 8E disp8 3 19 SZHPNC

SUB

Subtract, IY

Mode Opcode Operands Bytes Cycles Flags
(IY+d) FD 96 disp8 3 19 SZHPNC

SBC

Subtract carry, IY

Mode Opcode Operands Bytes Cycles Flags
A,(IY+d) FD 9E disp8 3 19 SZHPNC

AND

AND, IY

Mode Opcode Operands Bytes Cycles Flags
(IY+d) FD A6 disp8 3 19 SZHPNC

XOR

XOR, IY

Mode Opcode Operands Bytes Cycles Flags
(IY+d) FD AE disp8 3 19 SZHPNC

OR

OR, IY

Mode Opcode Operands Bytes Cycles Flags
(IY+d) FD B6 disp8 3 19 SZHPNC

CP

Compare, IY

Mode Opcode Operands Bytes Cycles Flags
(IY+d) FD BE disp8 3 19 SZHPNC

INC

Increment IY

Mode Opcode Operands Bytes Cycles Flags
IY FD 23 2 10
(IY+d) FD 34 disp8 3 23 SZHPN

DEC

Decrement IY

Mode Opcode Operands Bytes Cycles Flags
IY FD 2B 2 10
(IY+d) FD 35 disp8 3 23 SZHPN

PUSH

Push IY

Mode Opcode Operands Bytes Cycles Flags
IY FD E5 2 15

POP

Pop IY

Mode Opcode Operands Bytes Cycles Flags
IY FD E1 2 14

EX

Exchange IY

Mode Opcode Operands Bytes Cycles Flags
(SP),IY FD E3 2 23

JP

Jump IY

Mode Opcode Operands Bytes Cycles Flags
(IY) FD E9 2 8

LD

Load IY

Mode Opcode Operands Bytes Cycles Flags
IY,nn FD 21 imm16 4 14
(nn),IY FD 22 addr16 4 20
IY,(nn) FD 2A addr16 4 20
SP,IY FD F9 2 10
(IY+d),n FD 36 disp8, imm8 4 19
B,(IY+d) FD 46 disp8 3 19
C,(IY+d) FD 4E disp8 3 19
D,(IY+d) FD 56 disp8 3 19
E,(IY+d) FD 5E disp8 3 19
H,(IY+d) FD 66 disp8 3 19
L,(IY+d) FD 6E disp8 3 19
A,(IY+d) FD 7E disp8 3 19
(IY+d),B FD 70 disp8 3 19
(IY+d),C FD 71 disp8 3 19
(IY+d),D FD 72 disp8 3 19
(IY+d),E FD 73 disp8 3 19
(IY+d),H FD 74 disp8 3 19
(IY+d),L FD 75 disp8 3 19
(IY+d),A FD 77 disp8 3 19

RLC

Rotate left circular (IY+d)

Mode Opcode Operands Bytes Cycles Flags
(IY+d) FD CB .. 06 disp8 4 23 SZHPNC

RRC

Rotate right circular (IY+d)

Mode Opcode Operands Bytes Cycles Flags
(IY+d) FD CB .. 0E disp8 4 23 SZHPNC

RL

Rotate left (IY+d)

Mode Opcode Operands Bytes Cycles Flags
(IY+d) FD CB .. 16 disp8 4 23 SZHPNC

RR

Rotate right (IY+d)

Mode Opcode Operands Bytes Cycles Flags
(IY+d) FD CB .. 1E disp8 4 23 SZHPNC

SLA

Shift left arithmetic (IY+d)

Mode Opcode Operands Bytes Cycles Flags
(IY+d) FD CB .. 26 disp8 4 23 SZHPNC

SRA

Shift right arithmetic (IY+d)

Mode Opcode Operands Bytes Cycles Flags
(IY+d) FD CB .. 2E disp8 4 23 SZHPNC

SRL

Shift right logical (IY+d)

Mode Opcode Operands Bytes Cycles Flags
(IY+d) FD CB .. 3E disp8 4 23 SZHPNC

BIT

Test bit (IY+d)

Mode Opcode Operands Bytes Cycles Flags
0,(IY+d) FD CB .. 46 disp8 4 20 SZHPN
1,(IY+d) FD CB .. 4E disp8 4 20 SZHPN
2,(IY+d) FD CB .. 56 disp8 4 20 SZHPN
3,(IY+d) FD CB .. 5E disp8 4 20 SZHPN
4,(IY+d) FD CB .. 66 disp8 4 20 SZHPN
5,(IY+d) FD CB .. 6E disp8 4 20 SZHPN
6,(IY+d) FD CB .. 76 disp8 4 20 SZHPN
7,(IY+d) FD CB .. 7E disp8 4 20 SZHPN

RES

Reset bit (IY+d)

Mode Opcode Operands Bytes Cycles Flags
0,(IY+d) FD CB .. 86 disp8 4 23
1,(IY+d) FD CB .. 8E disp8 4 23
2,(IY+d) FD CB .. 96 disp8 4 23
3,(IY+d) FD CB .. 9E disp8 4 23
4,(IY+d) FD CB .. A6 disp8 4 23
5,(IY+d) FD CB .. AE disp8 4 23
6,(IY+d) FD CB .. B6 disp8 4 23
7,(IY+d) FD CB .. BE disp8 4 23

SET

Set bit (IY+d)

Mode Opcode Operands Bytes Cycles Flags
0,(IY+d) FD CB .. C6 disp8 4 23
1,(IY+d) FD CB .. CE disp8 4 23
2,(IY+d) FD CB .. D6 disp8 4 23
3,(IY+d) FD CB .. DE disp8 4 23
4,(IY+d) FD CB .. E6 disp8 4 23
5,(IY+d) FD CB .. EE disp8 4 23
6,(IY+d) FD CB .. F6 disp8 4 23
7,(IY+d) FD CB .. FE disp8 4 23

Machines

Sinclair ZX Spectrum, Amstrad CPC, MSX, NEC PC-8801, Sega Master System

Sources

Encodings on this page were taken from:

  • Programming the Z80, 2nd edition — Rodnay Zaks, 1980
  • Z80 Microcomputer Handbook — Sams, 1985